Half-bridge/gate drive heeeeelp!

Here's the situation in simplified schematic form, generate a high-efficiency sine wave at around 3-5MHz putting out about 5 watts into resistive load:

Just drive it like two half-bridges with appropriate logic-level wavaeforms (some dead-time) and if you look at the two switching nodes together on a plot you get the red/black waveform there under inductor L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle. in theory.

First attempt at it on a protoboard:

"it looks great in the sim" and the connection of the boost diodes to the switching nodes gives a nice ~12-13 volt Vdd to common rail above the lockout threshold for the flying driver's supply nodes and keeps all the component dissipation low.

Total miserable nightmare to get working right as a prototype, losing gate drivers for unknown reason, these chips seem way slower than the ~50n prop delay specified in the datasheet, can't get up to speed. I don't think this 4120 likes being driven the way it's connected here in reality and they're dying on me, or I've made an error in the implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive schemes for this, I'd like a cheaper faster and more rugged one, as someone mentioned I don't really need the ADuM4120's internal transformer isolation if I could find a good way to level-shift the incoming logic level drive appropriately to the negative rails the lower FETs have. Thanks

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bitrex
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I can envision a lot of DC circulating in addition to switching losses.

This will be difficult with mosfets and regular gate drivers, as you note. You might consider something simpler, like a single mosfet or SiC fet in a tuned class-C amp. RF stuff. One power part on a heat sink.

You could probably use some gate drivers, like IXDN602, as the output device itself if all you need is 5 watts. They are cheap and fast and handy for a lot more than gate driving.

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John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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John Larkin

Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if they'd like being paralleled...

This is my second idea for KISS-approach:

Use two non-isolated gate driver chips with like 10ns propagation delay. One of two shown. Keep the flying-boostrap connection the same. And "level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above the negative supplies on the primary side. But I think it's better than messing with four isolated drivers, I don't really need them for isolation just level-shifting.

Reply to
bitrex

I think the flying-diode connection to the opposing switching nodes helps there with negative feedback. If one side develops a DC-offset the boost gate-drive voltage on the opposing side increases or decreases to push it back

Reply to
bitrex

Oops, forgot to connect "HS" to the mid-point in that diagram

Reply to
bitrex

Data sheet says yes.

Two, or maybe 4, of them would be no big deal in space or cost.

How about a single half-bridge? Step up the voltage passively if you need to, transformer or resonant circuit.

We make simple transmission-line transformers, 2:1 step-up at 100 volts pulse out into 50 ohms and maybe 1 ns rise time.

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John Larkin         Highland Technology, Inc 
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Reply to
John Larkin

Or add a capacitor!

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John Larkin         Highland Technology, Inc 
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John Larkin

Where, in line with the Ls?

Reply to
bitrex

Yes.

Even a small duty cycle mismatch could pump a lot of DC current through those inductors.

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John Larkin         Highland Technology, Inc 
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John Larkin

I'll check if that stops it trashing gate drivers at least, the output stage can handle a bit of offset but it does look like the more fragile gate-driver FETs are going to be unhappy with that. They're thermally-limited but it probably can't react fast enough to big offset-related spikes. :(

Reply to
bitrex

The AD devices and FETs are too well-matched in the sim and as such the DC-problem doesn't obviously rear up.

Reply to
bitrex

We have a zillion of the IXYS drivers in stock. I could send you some. It's a Zen thing, the best way to design is not to design.

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John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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John Larkin

Thanks! but i don't see how to make it work in this configuration look like they have a common ground between sections.

That ADuM-BS is nice in theory because they take logic level on one side and HV on the other, don't have to think too hard about level-shifting the drive from the uP or whatever.

Reply to
bitrex

At ~5 watts into a load with the blocking caps in place and rails as shown in the sim at least the efficiency of this structure is ~90%

Reply to
bitrex

I meant to use them as the power output stages, not as gate drivers.

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John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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John Larkin

I understand, but still looks like a problem. there's two complimentary pairs in the same package but the input ground and the grounds of both low-side FETs are common.

Reply to
bitrex

Why do you need the funny voltage power rails? If you're making a sine wave let your output LC do the voltage transformation. Sounds like you're trying to make a sort of 80meter ham band QRP transmitter but using an SMPSU approach?

Did you rule out traditional push-pull (two low side n-ch devices) for some reason?

piglet

Reply to
piglet

Like using a center-tapped transformer, you mean?

Reply to
bitrex

Or at least a single positive supply.

If you are going to use discrete fets, it's easy to drive them if the sources are all ground.

Sloman will be happy to design a transformer for you.

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John Larkin         Highland Technology, Inc 

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Reply to
jlarkin

I agree, these negative rails are a pain. My alternative idea is to do something like this, four FETs and one phase of this:

I could keep the +25 and 25/2 rails for the top two FETs, and keep the drive logic the same as I have it I think. Use an off the shelf L and l:l transformer. The client would like to be able to raise and lower the output voltage in steps by adjusting the supply voltages in steps...maybe set a step-up ratio to the midpoint of the desired range, actually. 50-200V P2P

He likes that circuit very much.

Reply to
bitrex

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