In a mosfet half bridge, the on-coming switch Vds is held at the supply potential while reverse recovery current flows in the free-wheeling arrm's diode. There's nothing to stop gate voltage from exceeding the turn-on threshold by some volts as only Ciss is active.
When freewheeling Trr ends, The mosfet is already gate-enhanced to exceed the peak Irr. This may equal or exceed the inductive load current. The resulting dv/dt brings Crss into the act, but not in the tame manner of resistive load current. The gate voltage may actually be driven below a threshold of equilibrium by dv/dt induced gate currents, producing oscillatory behavior.
This appears to be agravated by buffered pull-down in the drive, even with a high impedance gate drive source.
Any advice on beating this? reduce the effectiveness of the pull-down buffer?
RL