See "FloppyDataExtractor.pdf" on the S.E.D/Schematics Page of my website.
I would call this a PJL, "Phase Jerk Loop" ;-)
I posted this in 1995, but came up with the idea some time between
1977-87 when I was Analog Guru at start-up OmniComp/GenRad.I have used this scheme since on a couple of much higher frequency clock synchronizers for satellite communications, etc.
Works just dandy for those situations where you have missing incoming clock pulses.
In this day of super high chip speeds it becomes trivial to capture high speed clocks. ...Jim Thompson