goofy PWM

make it balanced ?

-Lasse

The appnote is ST's AN4507, about PWM dithering. They reference only one paper, by Angel Peterchev, who was a student engineer in my lab for a few years. Here's his 2001 PESC paper on DropBox.

How about TI's DAC1220, 20-bits, 2ms to 0.012%, $9.

Read the paper. We squeezed the process into a tiny programmable logic device - an ICT7024 - like it says in the paper, and it took Paul Buggs a couple of days to get it to fit. Since then it should have got a lot easier

It's not something where a linear feedback shift register would be any help at all, unless you wanted to do each of the comparisons involved in serial rather than parallel logic, and why would you bother?

John Larkin wants to do a comparison every 50nsec on 20-bit long words, which would 2.5nsec per serial comparison - fine in ECLinPs, but much more expensive than programmable logic.

That would probably work. It has the filter built-in, which is its main advantage. Performance-wise, it's about a tie with what I could do with PWM.

It will need a triple or quad coupler, including the 2.5 MHz clock, no big deal. Too bad they didn't include an internal clock.

The PWM thing would be about $7 cheaper per channel. You never know how many channels you're gonna sell. 100? 20000?

Accuracy is remarkably good, but only after self-calibration. And - with my faith in TI - I'd worry that the calibration would only be good where it was easy to test.

Tricky, when it has to communicate with the rest of the world over a serial line.

It's not as if you spend a lot on development ...

Our rule was never to develop what you could buy. There are better ways to keep engineers busy than re-inventing the wheel.

The PWM will only be cheaper if you can get it to meet spec and the sales covers the NRE. Right now the NRE is an unknown quantity as is the sales volume it would seem. Then there is the opportunity cost of spending an unknown amount of time on developing the PWM approach, time you could spend on work with a known payoff.

BTW, you don't need an opto for the clock. The TI part can work with a crystal although that's pretty much a wash in most regards. Also, you only need one additional opto for each additional channel since the interface has chip selects. So you need 2 or 3 + N optos, not much more than the PWM approach if you have multiple channels per unit.

Nice thread, I don't have anything to add. I wanted to check my understanding. You chop up the PWM finer to make the LP filter easier. There's some error with the turn-on and turn-off time asymmetry in the opto-isolator. So you keep the number of edges (chunks) fixed. (Hmm, could be other on-off timing errors too.)

For accuracy it would be nice to have a symmetric opto-iso.

George H.

It's easier to optoisolate the clock. Getting crystals to work reliably with chips like that is always a hassle. The TI data sheet has the usual fuzzy advice about the crystal.

I usually buy oscillators, not crystals. The oscillators always oscillate.

Also, you

The channels need to be individually isolated. CS is optional on this chip, which would allow me to use 3 opto channels per DAC (clock, SPI clock, SPI data.)

So you need 2 or 3 + N optos, not much more

The low quantity price on that TI part isn't great. I'd probably never buy 1000 at a time.

The FPGA logic is about a wash: SPI or PWM, no big deal either way. The goofy PWM is more fun.

The DAC1220 has 16 registers to deal with! Not fun.

Yes. The alternate to the goofy non-equal pulses would be straight PWM with a higher clock frequency. 200 MHz is about the practical upper limit inside the FPGA, which gives 200 Hz plain PWM at 20 bits. That will get lowpass filtered to maybe 2 Hz net. Higher order filters would just accumulate delay. So, sneaky tricks are indicated.

We could do something else exotic, like use a SERDES channel to make PWM with 1 ns or better edge resolution, something like that. 1KHz straight PWM with 1 ns width resolution is 1 PPM. We've done the SERDES trick before; it's not bad.

I guess I'd let my FPGA folks decide which way to do it, SERDES or some goofy multi-pulse algorithm.

That translates to a little DC offset. There's no linearity error as long as I keep the edges away from one another.

The TI parts are capacitively coupled, and the ADI parts are magnetic. Most optos are slow and have nasty TCs. One TI coupler specs 2.5 ns max pulse width distortion, awfully good.

So you need isolated power for each channel? That's a lot more hassle than the optos.

Lol, 15 minutes with the data sheet and the simplest of state machines... also called a counter. Often chips like these default to a basic usable mode with no setup. But then you won't be doing the FPGA code anyway. Let someone who knows how decide if it is hard or not.

These are cute:

maybe add a common-mode choke or two to tame the switching noise.

Assuming the data sheet tells you all you need to know, and is right.

The digital interfaces and documentation of mixed-signal parts tends to be ghastly.

The SPI part is easy, since an ARM program would do all the detailed stuff. It's not a big deal to mash all those bits, just a nuisance.

We use one SPI DAC that has a control bit that switches the SPI clock from rising edge active to falling edge. The initial state is not defined. Think about that.

Really? This is four times the size of the DAC without the choke! I guess space is not a concern. I would think a device that only needs a few uAs could be powered with a very simple capacitive coupling, a few passives and a three pin regulator. Am I wrong about that? You can generate the square wave from any logic output. Or do you still need an opamp that uses a lot more power?

If you have that much trouble programming the part, let me know and I will be happy to do it for you. I'm pretty bored at the moment.

BTW, I did notice one section in this data sheet, "Brownouts and Power-On Reset". Seems the part can get into a state on brownout that you can't reset it from since there is no reset pin. They use a "reset pattern" on the SCLK pin which might not be recognized if it is brownout hung. I'll admit this sounds very goofy. The fix is to discharge the supply completely which shouldn't be a problem with your setup.

The fix for that dac edge problem was to make the data wide in time and pulse the clock, so that the part sees both edges on each data bit. Crazy.

If we use the TI dac, and programming it looks like work, I'll let you know. My c guy will just want to slam a struct full of setups at powerup time, then poke in DAC values later.

Typical for mixed-signal parts. Analog designers apparently can't do logic.

Sometimes the bugs are only implied in application examples or footnotes. Look for the ominous "For optimum operation..." phrases.

if you are not prepared to defend your position here I'm going to ignore it.

I don't see why that is so crazy. It might not work with an MCU SPI port which doesn't have that capability. Did anyone provide feedback about this? Likely all they needed to do was document the start up state. If that was not controlled they should rev the part and control it.

That's pretty much all you need to do. Seems to me the structure is a bit of overkill, but some folks like a lot of organization. In a case like this where the data is very unlikely to change over the course of the project, I would just define an array of words

They cheaped out on the internal reset and because of pin limitations (I assume), they don't have a spare for reset. I don't know why it didn't occur to someone on the crew that the logic could get in a state that wouldn't detect a sequence on the inputs.... that's what the reset is supposed to cure, duh. A simple mistake in an effort to stay in a 16 pin package. I'd say it was more inexperience than systemic incompetence.

John Larkin schreef op 05/29/2015 om 04:18 PM:

I had a similar problem where I had to spread normal pulses and pulses with a length N-1 over several periods for a DPLL design. I turns out that using the reversed bit order of the period counter does that nicely.

From a decade old memory: say you have 16 periods and 4 periods need to be extended. Reverse the bits of the counter and extend the period when the reversed counter is less than 4.

All you need to do to get a copy of the paper is to e-mail me at snipped-for-privacy@ieee.org

I don't see the point of repeating what I've long since published.

Higher order filters give more attenuation at higher frequencies, but with PWM the worst case gets to be the PWM repeat frequency - 200Hz in this case - and more than two or three poles isn't worth the effort

There's nothing goofy about using more than two transitions per PWM period. The more you divide up your marks and spaces, the lower the amplitude of the repetition rate ripple - 200Hz in this case. Breaking up your 1,000,000 clock edges into chunks that would mostly be 1024 clock edges long drops the worst case 200Hz ripple component by a factor of 1000, which helps the filter design no end.

There no linearity error except at the top and bottom ends where individual - nominally 1024 clock edge long - chunks start vanishing or fusing, so the number of transitions per cycle moves away from 2000 - at the bottom of the range, from 0% to 0.1% of full scale and at the top, from 99.9% of full scale to 100%.

You could always re-synchronise to a local clock on the other side of the isolation barrier ...