Anybody care to speculate about the most important aspects to consider when trying to achieve 98% efficiency in a low-power (20mW) boost converter? Most available step-up converter circuits seem to perform in the 85 to 90% region.
I'm finishing a PCB "test bed" layout, which allows jumper-selection of different inductors, synchronous switches, and adjustable controller parameters. I'm hoping not to forget something important before sending it off to the PCB house. Just for fun I thought I'd make it in the form of an Arduino shield; giving an option for the processor to control the parameters and take measurements.
For that efficiency and low power level, I would throw away regulation and go with a switched cap converter. I'm guessing that's out of the question here though.
For this board my first two guesses would be switches' gate charge losses and the inductor's DCR.
Sadly, your approach has an irony: the jumpers will add leakage inductance, which you'll have to identify as a source of loss. :-(
The quiescent current of the control circuit itself will be a considerable fraction of that, even for very-fine-feature-size ICs. Perhaps there are some energy-harvesting controllers that idle that low, but gee.
Is this from scratch, or testing commercial ICs?
Note that a synchronous converter needs to be very closely tuned. Nearly zero dead time. No time to let body diodes conduct (that's loss, and probably step recovery behavior too), no time to draw shoot-through current (which you'll want to assist by adding supply inductance). Few commercial controllers and regulators are designed this way, instead using a cautious ~30ns or so.
The Baxendall Class-D oscillator is self-resonant, so doesn't have to be "closely tuned" and switches when there is zero current through the switches, eliminating switching losses.
In the rudimentary MOS-FET-driven version
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about the only place to waste power is in the damping resistors on the MOS-FET gates, and the series resistance of the inductor and the transformer windings.
Keeping those losses low might bulk up the cores a bit.
Leakage inductance doesn't come into it
I've no idea whether it could make 98%, but Jim Williams got close to 95% with messier and cheaper circuits.
You might have have floating windings to drive synchronous inverter switches on the output, and might all end up a bit bulkier than Win has in mind.
Too many degrees of freedom to answer you Win--it depends very much on the Vout/Vin ratio, for one, and the absolute values of Vin and Vout, too.
E.g., I designed a 3uW boost (0.6-to-3V @ 1uA). I had to use all jelly-bean discretes since there were no Iq-suitable ICs, and BJTs due to the low input voltage. Efficiency was ~70%, IIRC.
Where the input voltage is low and currents high, switch saturation voltage is limiting. Where the output voltage is low, rectification losses are a pain; a Schottky diode's 5% loss was usually better than a synchronous rectifier at 6V output, after switching losses and rectifier drive and added complexity to gain perhaps 2% extra efficiency were factored in.
Breaking your problem into pieces, fundamentally, getting 98% overall efficiency is a matter of storing over 99% of the input energy in the inductor each time you charge it, and delivering over 99% of the stored energy to the load each flyback cycle.
Reducing further, charging, the inductor has to store at least 99 times the switch's gate drive, switching loss, and conduction losses. The inductor's d.c.r. loss factors in too. Core losses were minor, IME.
The same analysis can be applied to the flyback portion of the cycle, and the 2% loss budget can be distributed across the two phases as you see fit.
I suspect you'll find your parameters produce optimal efficiency with MOSFET switches infrequently operated, large-cored high-valued inductors, short bursts or single-cycles of activity, and long periods quiescent. But YMMV.
Thanks, your comments are right on target and can kick off the discussion I was hoping to see. I'll get into that conversation tomorrow. But in the meantime I've updated my draft schematic and PCB layout, adding more features and items relevant to the discussion.
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Here's an inducement: anyone who'd like to experiment with issues and concepts embedded in the RIS-767 board, I'll send you two blank PCBs to play with. You just have to talk about what you learn, should you get around to learning anything!
You're going to wind up with a while bunch of trade-offs, such as larger and larger FETs reduce conduction loss, but take more power to drive; higher inductance lowers i^2*r losses from peak currents, but increases the parasitic capacitance you have to drive, etc.
I designed a ~120W two-stage switcher a couple years ago where maximum efficiency was essential for heat management, as the unit was in still air in a small, sealed box, & subject to heating by direct sunlight. I wrote a spreadsheet to model the losses given the various parameters, which helped me choose FETs & make other decisions. A little messy and crude, but predicted actual losses quite accurately.
At 20mW you'll have the advantage of almost ideal capacitors and plenty of capacitance for storage.
At Rds(on)=.065 ohms, the FDN337 looks like overkill.
Please pardon me as I doodle here...
A few calculations:
1) Conduction loss. For 20mW @ n=98%, total loss budget is 400uW. Assuming Vin=4V and n=98%, i.in(avg)=5mA; i^2 * Rds(on) = 1.6uW for a perfect, zero-ripple-current infinitely-fast continuous-mode switcher, or four times that for a boundary-mode design with twice the peak iL.
2) Gate drive loss: If the gate charge is 7nC driven at 4V, and we start off allocating it 1/10th the total loss budget...that's 40uW @ 4V, or 10uA(avg), which means we could afford to drive it at f=i/2q=700Hz. Ballpark.
3) Output capacitance: Assuming Vout=8V (I don't know the actual), 20mW is 2.5mA load. For 50mV output ripple and 700Hz update rate, we calculate the necessary filter cap: C = i * dt / dV = 2.5mA*(1/700)s / 50mV = 70uF.
4) If we budgeted a maximum permissible conduction loss, i^2 * ( Vds(on) + dcr(L) ), that fixes a max. peak current i.pk. From i.pk and Vin and our output ripple voltage spec. and the output capacitance, we can compute the minimum inductor value. The inductor value and i.pk then give us the inductor charging time, i.e., the switch on-time.
Interesting--the ripple voltage depends ultimately on the available output capacitance. After picking a maximal practical capacitor, given the output capacitance available, the maximum allowable output ripple voltage, and the inductor value, you can calculate the peak inductor current needed for any given switching frequency, and from that, the FET conduction losses.
Oh, I forgot to factor in that FET conduction losses are reduced by the duty factor, both for the main switch and the synchronous rectifier; dcr(L) matters twice, both for charging and discharging.
All this doodling suggests the start of a spreadsheet to me with Vin, Vout, n, P, Vripple, Rds(on), Qg, dcr(L), and a few other inputs...
I'm sorry for not yet taking the time to introduce and discuss my project in more detail. I'm still postponing that, but will say a few quick things:
1) My initial and primary goal is to optimize a 2.0 to 2.4-volt boost converter running at 10mA, or 24mW, with no more than 0.5mW of loss. For that purpose the small TS5A3159 spdt switch, 0.8 ohms and low capacitance, should be good. There are also even smaller parts in the same sot-23 package layout.
2) Other choices on the PCB are to allow for playing around with higher optimal currents. I figured, once the generalized PWM hardware was in place, why not add a provision for larger switches and inductors. I'm going to add to the discrete MOSFET footprint choices.
3) Since this is just a test-bed breadboard, I separated the power consumption for PWM control and driving FETs, from the inductor and switch losses. The switch losses still include f C V^2 of switch capacitance loss, but not the gate-driving power consumption.
4) I'm still looking hard for good inductor candidates to add to the PCB. Most have appallingly-high losses, and unfortunately these are not detailed on their datasheets.
Large inductor and slow switching speed? ...Jim Thompson
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What if the gate is in a series-resonant tank? The L stores the necessary energy for the next phase, instead of it being lost. You only lose due to the R(L) and the gate resistance.
Yes, you can recycle the gate drive that way. But if the gate drive loss is small, that would add a lot of complexity. High-power converters can even recycle their leakage inductance's stored energy--Tim Wescott gave it a whirl a ways back IIRC.
I've not thought about resonant converters for decades--don't even they want a square gate drive, to keep the switches from going linear?
I'm curious about Win's application. Normally 20mW is not valuable enough an amount of energy to throw a lot of expensive parts at. His must be a cubesat, or some super-demanding application.
Schematic and PCB layout further updated, adding a wider range of test component footprints. Now have 20 configuration jumpers, plus three pots, and 12 optional connections to an Arduino. The board can be populated and run in stripped-down fashion (and PCB size appropriately sheared), or it can be heavily populated, with components and details selected by moving header jumpers.
I've been concentrating on inductors lately, and am almost ready to order the PCB. Anybody wants two blanks, let me know so I can increase my order.
So far measuring commercial inductors, that's all I've come up with. Most have unacceptable losses at high frequencies. One that should work is a TDK SL1720, a large 17mm D x 20mm H size. The 1.5mH part is rated at 1 amp, and DCR = 0.86 ohms. Its AC resistance measures 3 ohms at 20kHz. With D = 17% and ON time 8.4us, dI = 8.4us 2.0V/1.5mH = 11 mApp, and the I^2 R loss would be about 0.125W, or 0.6% of my 24mW power. Wait, that seems too low.
I'd like to be able to scale this to higher frequencies, e.g. 100uH at 300kHz. Could be, I have some candidate parts to test.
In the world of solar-energy-conversion research, every percent counts. Players struggle for every 1 to 2% advantage. If a test system size is 20mW, then 1% is 200uW. My associate's lab system is at that level. I'm fighting losses converting 0.7 - 2.0V to 2.40V for an electrochemical cell. So if I take more than 2% away from his process, that's serious business! But in the meantime, 98% is also interesting challenge.** If we can do this without special stuff, that'll be great!
I'm not so sure about that. There are easier ways of getting more power out of setup than raising the efficiency from 95% to 98%, and usually easier w ays of limiting the temperature rise in the inverter. Diminishing returns d efinitely start setting in hard when you get to 90% efficiency.
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