Dual MOSFETS Configuration

(schematics)

they are two and two parallel to increase current handling, assuming they share the current ....

-Lasse

Hi,

Will the HIP 4081A chip be able to drive the larger input capacitance of two MOSFETS in parallel? jess

MOSFETS in parallel?

The way to find out such things is via the datasheets. The IRF has about

5500pF per device, so 11000pF for two:

Then you look at the HIP datasheet:

It has high and low level output voltages at 100mA and those do not look very good IMHO. So at high frequencies it'll all become quite lossy and toasty. The switching frequency is a key parameter here. There are better drivers these days, CMOS-based. You can get them with and without boost circuit. Micrel, Microchip, TI, and so on.

--
Regards, Joerg

http://www.analogconsultants.com/

MOSFETS in parallel?

I use gate charge to end of plateau, if the datasheet gives it. Otherwise, I use total gate charge knowing that it is worst case.

Actually, the chip specs say that it can supply over 1A peak minimum.

Gate charge of the two FETs in parallel is about 340nC.

Assuming 1A of charging current, the parallel combo should switch in about 340nC/1A or about 340ns. That won't happen because rise time is

190ns, but it tells me that driving the two FETs in parallel is okey-dokey. Maybe they will switch in, say, 600ns.

Cheers, John S

(schematics)

Its a full bridge so you'll need at least 4 devices. Maybe the designer is trying to share the current. In my experience a MOSFET with a lower RDSon isn't always more efficient because the gate capacitance is much larger so it switches slower.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Depends on how often. There comes a point where it might unsolder itself. Personally I'd use a driver with more gusto.

That is half an eternity :-)

--
Regards, Joerg

http://www.analogconsultants.com/

[...]

Just took another look. The FETs might also blow up with such sluggish transition times. It says 31.25kHz in the manual so that's 16usec per half-cycle. 600nsec means the FETs realistically spend around 2-3% of the time in a somewhat linear range ... phsss ... poof ... *KABLAM*

The author mentions up to 500kHz. Jessica: Don't do that!

--
Regards, Joerg

http://www.analogconsultants.com/

IIRC the HIP4081 has dead-time control. I've used it in a class D amplifier at 300kHz. It needed a heatsink to be on the safe side.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Sure, but dead-time control does not help with the sluggish turn-on and turn-off. If there is a big motor connected it could result in the FETs becoming really toasty. Normally you want to switch as fast as possible and then muffle the EMI on the motor leads.

--
Regards, Joerg

http://www.analogconsultants.com/

I recently made a cute 50W DC-DC supply that burns maybe a couple watts total. Gate drive is discrete, 2N3904s -- maybe 200mA peak, putting the gate rise/fall time around 150ns. Of that, maybe 40ns is spent in Miller effect. The actual output transition occurs in about 20ns, at least for voltage (the current transition is probably slower, but the snubber helps absorb that).

What surprised me about this supply is, schottky diodes are *worse* than junction diodes in this application because their sharp C-V curve looks like really bad reverse recovery. Junction diodes

(schematics)

It still a 4 Transistor bridge, they are simply pairing them for higher current handling.

Jamie

Ok, but this guy in the paper is taking up to 70 amps continuous current on a 24V motor. That's some serious power.

Si-diodes are often dissed without giving them a fair shot at it. With slow converters they can be ok, just not when things run at a MHz or higher.

--
Regards, Joerg

http://www.analogconsultants.com/

I've found schotty diodes to be an hindrance because it's hard to find them in low C.

I do however, like to use them for the lower forward voltage and switching times, even though we must still work with that larger of average C that is found in them.

Jamie

MOSFETS in parallel?

I used the HIP4081 for a project 10 years ago at 100kHz switching frequency for a offline SMPS with smaller MOSFETs than described here. It became very hot and I had to change to another type. It is really not meant to run at very high frequencies

Cheers

Klaus

MOSFETS in parallel?

That's why I was a bit surprised to see "up to 500kHz" in that paper. I am almost sure the author just wrote that without trying it for more than a few seconds. Else he'd have seen the chip unsolder itself :-)

--
Regards, Joerg

http://www.analogconsultants.com/

I just took another look, too, and I don't know where I got that 190ns because the data sheet says rise and fall times are 35ns. The chip can supply a minimum of 1.3A minimum for switching.

Additionally, I looked at the FET gate charge graph and saw that the charge is about 105nC to the end of the plateau, making the total charge for two FETs about 210nC.

So, it looks like 210nC/1.3A is about 162ns to get the FETs switched. Adding the chip's 35ns puts the switching time right at 200ns.

Knowing the Id and Vds during this period can give a crude estimate of the switching power dissipation.

The chip will dissipate FCV^2. Using the total gate charge of 340nC, F of 100kHz, 12V on the gate, I get .4W per bridge arm. That means about .8W dissipation for the chip. The SOIC package is spec'd at 85C/W, so that will raise the chip temperature about 35C above ambient.

If I didn't make a mistake somewhere.

John S

Looking at the paper referenced by the OP, I see 70A and 48V shown as continuous current and supply voltage.

Estimating 35A at 24V gives 840W for peak power dissipation. Estimating the power curve to be triangular gives 200ns*840 joules (two transitions per cycle per bridge arm). At 100kHz, then, the power is

100kHz*200ns*840 or 16.8W per bridge arm. Two FETs per arm means each FET is dissipating 8.4W due to switching only.

I should have completed the above with a conduction loss estimate. Rds is .0025ohms (two FETs in parallel) and continuous current is 70A. But the current is 50% duty cycle thru each bridge arm, so the RMS current is about 50A. This gives 6.25W dissipation per arm or 3.2W per FET.

Wow! Switching losses are almost 3x the conduction losses.

If I didn't make a mistake somewhere.

John S

two MOSFETS in parallel?

This might be a good time to add a PNP-NPN totem pole pass transistor boost circuit to the HIP's output.

We used the HIP drivers in the 1990s and found that they really weren't the best gate drivers for apps that need a lot of reliability. They're just "OK".

boB