1. Home
  2. Electronics Design
  3. FET capacitance lies?

FET capacitance lies?

Does anyone have corroborating Coss vs. Vds data they're measured from various transistors?

Case study: STP19NM50N. Datasheet shows a rather precipitous drop in Coss vs. Vds. I'm getting behavior in a circuit which is inconsistent with this. So I measured, using a pulsed method (apply CCS, measure dV/dt):

formatting link
Looks like a two exponent curve, probably consistent with Super Junction design or whatever.

The datasheet has a rather awkward curve:

formatting link
I note that their graph appears to be drawn with a couple of bezier segments, which could simply be poorly adjusted. An engineer would hope for better, though.

Here's an overlay comparison of the data:

formatting link
Surprisingly good agreement under 20V, then something goes wrong...

Limitations: the method appears to have acceptable resolution at low voltages. I didn't crank it down to measure milivolts, so the lowest points (off scale, not shown) are buried in quantization noise. It doesn't measure very well under 100pF, since the CCS itself (a power PNP BJT) is somewhere around there (if I can trust the datasheet, it should be under 20pF at these voltages, though). Early effect shouldn't be a big deal, since it's a cascode CCS. Values at more than 100V or so aren't reliable because of Ccb rising as it begins to approach saturation (the CCS was suppled from 130V), and maybe gain reduction or Miller effect or something: this explains the rising tail in the data. Dynamic gain shouldn't be a terribly big problem, because the whole rising edge took

70us; a measurement on an IGBT shows reasonable agreement with published data, and that produced a 30us edge.

Surveying a number of similar products, ambiguous results are seen. ST and IR datasheets seem to show steps more often than others. IXYS almost never. Infineon sometimes shows one or the other, but sometimes also plots full range data on a linear axis, so all the interesting sub-50V behavior is squished away (perhaps they're trying to hide artifacts such as these?).

Tim

--
Deep Friar: a very philosophical monk. 
Website: http://seventransistorlabs.com
Reply to
Tim Williams
Loading thread data ...

formatting link

  • So far so good; talking about FETs..
  • not a fet------------------------------------------------------------^
  • not a fet---------------------------------^
  • not a fet------------^
  • a 3rd beastie--------------^
  • Back to FETs..

Reply to
Robert Baer

formatting link

Biggest problem with commercially available discrete FET models is that the "LEVEL =" is rarely above LEVEL = 3... many just LEVEL = 1 (school boy levels). Thus the models have all kinds of errors.

For my chip designs I always use some version of BSIM3v3 or above. If discrete's were modeled to that level, you'd have no problems.

BTW, "Early Effect" in BJT's has an equivalent in MOS, "Channel-Length Modulation"... same effect: slope to the curves rather than flat versus voltage. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| Phoenix, Arizona  85048    Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

formatting link

Somewhere back in time, when Winfield Hill still posted here, we discussed 2N7000 models and how they were lacking. I vaguely recall making a fairly decent fit of a BSIM3v3 model by scaling some I/C models I had. Showed the gate charge plateau and everything. I'll try to recall what I called the file. (My main problem is I forget where I file and what I name, so I spend days trying to find things ;-) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| Phoenix, Arizona  85048    Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

formatting link

I knew about the slope to the I/V curves in FETs, and knew that it was not due to "early Effect". Thanks for the enlightment.

Reply to
Robert Baer

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

2N7000 models are weird. Some show rg = 243 ohms or something like that (way too slow versus actual devices), others none at all (= infinitely fast, also a lie).

The STP28NM50N model in question is LEVEL=3, so at least they did that. But the Cdss model is nonexistent.

Tim

--
Deep Friar: a very philosophical monk. 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

I'm talking about FETs, do you have anything to say about them?

Yes....and? It's called a test circuit, Bob.

Still talking about the test circuit, Bob... it's called a "Limitations Section", a standard format, look it up.

Back to.... nonsense?

Tim

--
Deep Friar: a very philosophical monk. 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.