fast pulse on ribbon cable

søndag den 23. maj 2021 kl. 02.36.56 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

how about a SATA cable? I've also seen several PCIe extenders using a USB3 cable and connectors

both are two pairs and grounds that should be good for several Ghz

We could use a usb C connector on each board and a short cable. But the C-to-C cables seem to be charging cables, probably not good for fast signals.

USB data cables rarely have the same connector on both ends. Never?

søndag den 23. maj 2021 kl. 03.06.27 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

seems like USB3 is quite common with USB-A at both ends, that's also the ones I've seen used for PCIe extenders

perhaps SATA or ESATA data cable.

It's got a spare lane that you don't need but it's commodity PC hardware, so competitively priced and should work better than an unshielded ribbon.

Usually manufactured sockets are used, but yeah the springs are in the plug, so it could work with an edge connector.

eg: socket drawing

On Saturday, 22 May 2021 at 17:36:56 UTC-7, snipped-for-privacy@highlandsniptechnology.com wrote: ...

We often use Samtec connectors and cables for similar applications.

For high bandwidth with excellent signal integrity the sub-miniature coax assemblies work well.

Bandwidths up to 28GHz.

Thanks.

I'll have a small PC board with a photodiode and a comparator, and want to fan that diff PECL trigger pulse out to a few other boards. Each connection is just one signal pair. I need a tiny equivalent twinax connector.

Something sort of like this:

Regular ribbon cable is probably OK for sending a single rising edge a couple of feet. The rest of the pulse can be arbitrarily ugly.

I should TDR a pair of PCBs with traces/connectors/cables.

Can you do two copper layers? A common form is a crossed quad:

gggPNggg gggNPggg

Being a quadrapole, the fields drop off quickly away from the quad.

Joe Gwinn

TI discusses LVDS over ribbon cable here:

Intel talks about LVDS over standard ribbon cable here:

-Jim M.

We usually avoid stackups that have adjacent signal layers. We alternate signal and ground/power planes to reduce crosstalk.

But I was thinking about ribbon cable signals as regards the ggPNgg thing.

My pseudo-thinking was that ribbon cable pattern

ggPNgg

concentrates current in the tiny bit of dielectric between the signal traces, which might increase both dielectric and skin losses.

ggPPggNNgg

moves more of the field into air and has more copper, so maybe less skin loss.

This looks better:

The flop resets itself, becomes a one-shot, stretching the picoseconds-wide optical trigger. Gotta test that. Some gates hang up if you connect an output to reset, but this should be OK. An EP gate has a lot of gain and the RLC thing helps too.

snipped-for-privacy@highlandsniptechnology.com

Hello,

we do fast synchronising and triggering with LVPECL too.

An example: Resync module under test (1 channel, 2nd version)

As can be seen clearly, a ~5cm stub (SMA-Tee, connectors, short symmetric board connections to the receiver and back) will act catastrophically on sub 100ps-edges. So, for low phase noise we use "good" coaxials only, driven by the old but good EP89. The first LVPECL receivers were EP11, the module in the picture used NB6L11 (unfortunately obsolete), the next version will use ADCLK925 or its derivatives. All high speed signals are routed in front of the modules, the ribbon backplane carrys digitals and power only. For longer distances or if the signal has to put into another cabinet, we use Fibers, consequently.

Which advantage has the -1.5V VEE? I use a 3-resistor-termination, routed through the receiver's inputs.

All I need is a single rising edge as a trigger, at kilohertz rep-rates. It might even be better to use slower cable drivers. I need to try this. But I think that we can maintain good signal integrity for single-source single-load runs. The ribbon cable connectors would be critical. I'll have to do a proto board and test it.

The ADCLK part is interesting: it looks like it has almost-full ECL output swing, unusual for fast parts. It's enough to drive a phemt.

Some of the laser drivers make really fast edges with big swings, like over a volt in 25 ps. They might be good line drivers.

If I use the diff clock input as a comparator, it gives me a wider input common-mode range. I'd still need to be concerned about the photodiode pulling the input above 3.3. Maybe the comparator version is safer, if a bit slower.

What is that NB6L110 part? It doesn't google.

We used the EPT21 and it was horrible. Slow and shocking amounts of jitter. LVDS line receivers are cheaper and much better.

All those jumper options and esd diodes will slow things down a little. You can do effective jumper options with surface-mount resistors or caps whose pads disappear into wide traces if they are not installed.

I get the feeling that not many people do this sort of picosecond time-domain design. The telecom people just throw equalizers at everything.

Sorry, that was the ELT21.

Still, an LVDS receiver might be better.

Here's a comparison

As expected from advanced electromagnetic theory/wild guessing, the double wire thing is lower impedance and faster rise time. It's a good model for

ggPPggNNgg

snipped-for-privacy@highlandsniptechnology.com schrieb am Montag, 24. Mai 2021 um 18:14:36 UTC+2:

Slew rate translates into phase noise --> should be steep enough.

We tried it 10 years ago already with good results. See:

We used a fast ADCMP at first in a "simple" TTL-fanout. It's trigger level and Hysteresis seemed to shift a lot with frequency as I believe to remember. Better to use LVPECL, if possible.

NB6L11D

This part is a LVPECL to TTL translator. Use it for that, only for that, application. We used it as a driver for the monoflop to visualise input pulses only.

The ESD protection _is_ necessary in our labs. Many people don't want to accept this, I know... I used low-cap TVS. The 2mm-jumpers are user-settable, for DC/AC, single-ended/differential, termination. Soldering is too much effort. It's not optimal, but works.

For phase noise results you might have a look to Abb. 4.9 and 4.10 in comparison to 4.8:

Cheers, Timo

Even cmos-speed edges can have sub-ps jitter. We've got down to about

USB c connectors and cables might be interesting too.

I think we'll use RJ45 connectors and thin CAT6 cables. One pair can be our diff PECL trigger, and the rest can be power supplies or something. The thin ethernet cables are nice.