Here's our little fiberoptic transceiver box in optical loopback mode.
The upper trace is the 1.2 GHz clock and the lower ones are the receiver differential outputs, at infinite persistance for about an hour. The TX data is a 127-bit pseudorandom digital data stream, from the back of the SRS box.
This is a telecom trick to look for ISI, inter-symbol interferance, and noise. The "eyes" should be wide open. This board suffers from FR4 losses and a tiny bit of design stupidity, so the next rev should be faster and cleaner.
My first (and so far only) customer will run at that rate, 1.2 Gbps, so he's OK. But I'm using a 10G SFP module, and my board is clearly limiting the data rate. Since I have a bug in the LED signal detectors (fixed by a kluge) I may as well spin the board and try to speed it up, for other possible users.
That SRS clock generator only goes to 2 GHz, and the PRBS option breaks before that. So I need a faster data source.
I bought a couple of cheap RF signal generators from Amazon, and maybe I'll make a little discriminator/fanout board to make nice differential logic signals and a pseudorandom sequence.
This should arrive tomorrow:
That will be interesting. A 2^7-1 sequence, which is commmon, takes 7 flipflops and one XOR gate, at about $20 each for NB7 series logic. I could get to 6 GHz, 12 GBPS, except for the XOR prop delay. Maybe there's a hack for that somehow. Pipeline the XOR feeedback? The mind boggles.
An FPGA could do serdes at 5 or 10 GBPS or even more, but that would be a bigger project than slapping a few flops on a board.
John Larkin Highland Technology, Inc
Science teaches us to doubt.
Am 22.10.20 um 18:08 schrieb firstname.lastname@example.org:
One should not underestimate the possible run lengths. We had a recurring bit error with overnight runs when developping our 10 GHz XFP transceivers. That caused a month-long delay, and each test result and changes had to be communicated to the customer, aarrghh..
I had the order to make sure that even the CEO would not take his cell phone into the lab. Me, an external freelancer. Not even inside the pecking order. And it happened. :-)
It turned out that someone had decided that 10n coupling capacitors were enough at 10 GBit/s because they visually fitted smoother into the 50 Ohm microstrip, from 100n before.
No, they were too small. Abt. 1 bit error per day.
The mother company decided later that fiber optics was not a core competence for a semiconductor maker and sold the farm to someone in San Jose. I was there some weeks for tech transfer, which was kinda interesting. In retrospect, the mother company was wrong, but then it's an uphill battle when you are a latecomer to the field.
Their pulse generators, and the opportunity to remove some sampling scope comparisons from the web site,