Ethernet+FPGA

Why don't use a Xilinx Virtex-4FX12?

Marco

as an

Ethernet LAN

I've seen such a project somewhere. Try opencores.org first.

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as an

Ethernet LAN

It should work in theory with 10Base-T, you might.. get away with 100Base-T. But I wouldn't be suprised by a "dead on arrival" ;)

I would like to use another vendor for other reasons so I need to design custom VHDL Ethernet stuff.

I am not worried about it, just wondering how to interface the LAN transformer from the FPGA I/Os.

Thanks Marco,

(such as an

Ethernet LAN

Thanks Nico,

I already checked opencores before posting this. Despite there is an Ethernet MAC controller project I wasn't able to find the full schematic description on how to interface the FPGA I/Os to the LAN Transformer.

The OpenCores Ethernet MAC connects to a "PHY" through the MII port. The "PHY" (physical interface) is the one that connects to the magnetics ("LAN Transformer").

So you'll need an FPGA+PHY+Magnetics.

John.

Thanks John,

What about the posibility of desiging your own PHY using VHDL+differential I/Os or specific analogic drivers?

It is not easy to find a distributor in Europe for small quantities (at least at a reasonable price).

Regards, Mario

I think several companies make PHYs now so that might help. PHYtec is one, SMSC might, have you checked around?

It's possible to make the PHY using an FPGA+discrete logic but I think it will be very hard. The Ethernet signals are multi-level and the PHYs typically have some kind of DLL/PLL architecture to synchronize with the data stream. It's not trivial to implement that.

I've thought about doing the same thing (more from an academic perspective) but that didn't really go anywhere.

You might want to pose your questions on FPGA related Ethernet issues to this newsgroup:

comp.arch.fpga

FPGA related issues are discussed there.

I check that group too :)

Regards, John.

(such as an

Ethernet LAN

For the output just use two cmos outputs to drive the transformer, for the reciever LVDS would probably work

-Lasse

Mario,

see fpga4fun.com, this guy beat you to it.

You could probably do 10Base-T transmit maybe 10Base-T receive but not

100Base-T and certainly not 1000Base-T. 10Base-T is manchester encoded. This is easy to generate and easy to decode. The device transmits only when a frame is being transmitted.

Even if you did not hit the 802.3 IEEE spec of around 5V output,(see section 14 of 802.3 I forget the exact subclause) most 10Base-T receivers would receive it as a valid signal. On the receive side, I don't know FPGAs too well. You would want use something like a schmidtt trigger at the pad..

100Base-T uses MLT-3 signaling, and transmits continuously on the TX pair since it recovers the clock from the waveform.

1000Base-T uses MLT-3 and PAM-5 signaling on all 4 pairs in both directions and requires lots of DSP to cancel out cross talk from other pairs and a sophisticated analog front end to convert the PAM signal to digital. Not possible.

regards. Kadir "Solid Gold" Suleyman

Mario Emmanuel wrote:

(such as an

Ethernet LAN

ISTR that 100basetx uses 25MSymbols/s at 4 levels AM for 100MBits/s signaling rate. AM direct from any logic levels seems alien somehow.

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 JosephKK
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if it is just for a one-off for fun project, I guess it might be doable with two LVDS inputs biased at the midpoints of 0 to -1 and 0 to +1

Tx could be done with some resistor and maybe two cmos outputs

I'm tempted to try it out :)

-Lasse