Oh. If both clock inputs are internally terminated, the simplest thing might to be to use an active buffer, an lvds-lvds part with two differential outputs. It could be a dual buffer or one of the fanout things with one input and multiple outputs. Four resistors at the pecl output would pull down the pecl and shift the dc level down to make the lvds buffer inputs all nice and legal. Then just route pairs from each lvds output to the Vertex clock inputs.
Check TI and National for apropriate lvds buffers. You'll need some software to calculate the differential trace impedances, Txline maybe.
I have previously posted on the differential input circuit that we (Xilinx) use.
I will repeat what I have said before: the differential input circuit is a full CMOS differential comparator. It will operate (function) from rail to rail on its inputs. Its performance has only been characterized for LVDS, and low voltage LVPECL common mode voltages and swings.
Now for the new part: there are no configuration bits to select anything. The comparator is the comparator, and it is the same circuit regardless of standard selected. If it is differential, it is the same circuit.
I have a perl script I posted some time ago that calculates differential impedance (there's a bug I have never fixed in the propagation velocity, though).
I've used this a number of times and empirically it agrees with the board manufacturer's data when they calculate the requirements for me.
# main print "\\n\\n"; print "Impedance calculator\\n\\n"; print "Source material:\\n Johnson & Graham, "; print "\\"High-Speed Digital Design.\\" 1993. Appendix C.\\n"; print "Differential impedance calculations based on empirical data\\n"; { my ($choice); do { print "\\nEnter S for stripline, M for microstrip, X to exit : "; $entry = ; chomp $entry; $choice = uc $entry unless $entry eq ""; print "\\n";
if ($choice eq "S") { STRIPLINE(); }
if ($choice eq "M") { MICROSTRIP(); } } until ($choice eq "X") }
One caution, most Xilinx LVDS inputs have a Cin of around 8-12 pF (single ended), which will cause horrible {re}reflections when driven directly in a multidrop topology from a fast ECL driver- unless those MGT clock inputs have much better Cin than the regular LVDS inputs.
Given the physical size of an FX60 package, there's likely to be enough distance between the two inputs to create a ledge or double clock with both inputs hanging off of the same net like that.
The fanout buffer is probably the best solution, but if I had to make it work driving two 10 pF inputs with internal Rterm from a single net, I'd probably try series R's at each clock input to form a higher impedance line tap/divider coupling a portion of the signal off of an externally end-terminated net.
other related FPGA LVDS notes:
- Spartan 3E LVDS inputs have a much improved Cin of around 3 pF
- Xilinx common mode input range with internal terminations: Although the LVDS inputs WITHOUT internal termination have a wide common mode range, the internally terminated variants (DIFF_TERM, DT) apparently are restricted to the much narrower common mode range of the associated differential OUTPUT standard to meet the specified internal termination tolerance
- resistive ECL level shifts for solitary FPGA LVDS inputs: When driving a single LVDS input, I usually use something like Fig. 15 of AN1568, which creates the shift with a tapped pulldown: -
formatting link
Plus additional provision for a series Rs from each junction, letting you tweak the back termination to match the line.
Those resistors can then all be placed right at the driver, far, far away from the cluttered BGA breakout pattern, with the typical LVDS 100 ohm Rdiff at the receiver input.
I will look into that. From what I know about the design, the only way to reduce the C is to leave out the LVDS output driver (0.5pF less), or make the IO drive strength smaller. Until we drop the high output standards, the C is unlikely to get any smaller (just physics of a general purpose pin). It may be that 3E drops some of these (I will check).
The Vref pins do not have any more load, until they are programmed to be a Vref, so we do not specify their C as a Vref (as the recommendation is to put a 0.1uF as close as possible to the Vref pin anyway).
Sometimes a missing specification is just something not needed.
But, if you filed it as a case, you should have received a reply as to why the specification did not require an update. Case #?
The simplified S3E I/O drops DCI and some of the higher drive standards vs. S3, and adds DIFF_TERM support.
Some inputs, such as global clocks or the MGT clock inputs of this thread, are likely to differ from general I/O, but are not documented as such in that single datasheet spec, nor in the IBIS files.
If the "perhaps" and the smiley didn't give it away, that was intended as a humorous observation for those of us who have filed WebCases.
That would make sense (dropping a low voltage strong standard reduces pin C). Dropping DCI would hardly save anything except area, however.
I will take it that you did not file a webcase. With a webcase number, it could be tracked and solved, or escalated (and solved). Or even reported to myself or Peter (as some have done).
Now that Spartan has "grown up", they are making their own decisions as to what to spend their silicon on, so I have lost track of some of their features. I should not have replied for them, as I really don't know what they are doing (without asking).
OK, now I see it. Spartan 3/3E/3A dropped HSTL IV, which is a 48 mA drive strength standard. III is 24 mA. That means the area required is cut in half, so the C could be half that of the Virtex series IOB's (that have HSTL IV).
If you look at the available S3E TTL/LVCMOS drive strengths, they are mostly around half of the S3 max strengths.
Sym>
Not yet, only took some initial measurements on an eval board of an I/O capable global clock pair in a FT256 package, which seemed in line with a ~3 pF Cin.
Note that many of those input only pins don't travel in pairs, and they also lack the internal termination feature.
I also haven't spotted any detail on those, or any limits for the S3E diff_term range.
BTW, if you check the S3A datasheet, they provide better numbers for the DIFF_TERM range and spec them for usage at 3.3V VCCIO; they've also gone to a top/bottom left/right split between the "goes to eleven" drivers and the lightweight S3E versions.
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