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I'm not sure I understand your questions. The ECC circuit will detect and correct 1 bit errors in each 64 bit word using 8 bits of ECC code. The mem ory interface has 72 data I/Os for these bits and transfers two words on ev ery clock cycle, one on the rising edge and one on the falling edge. Inter nally it is typical for the logic driving this to run at twice the external clock rate. Or I have seen designs that run at the same clock rate but us e two lanes of processing.
Is that more clear?
Rick C.