It was initially presumed that the DC reference of the individual ADCs was exhibiting a regulation effect as the input signal was biased positive for position in the GUI. The waveforms 120107a through C show that the loading effect depends on whether or not the biased input varies from half-reference levels. At midpoint position in the GUI, no reference loading occurs, dependant upon the stiffness of reference decoupling.
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A unipolar loading effect could have been compensated fairly simply by using the ADC outputs themselves to contribute reference bias, as the ADC output is positive logic and the originally noted reference regulation was negative. It's possible that the same compensation is still viable. Will let you know.
Non-linearity of the effect of GUI positioning on ADC reference, for static 0Vdc signal levels is illustrated graphically in:
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With respect to the midscreen position, none of this static variation exceeds 2.5%.
Although the effect seems magnified by signals that do not deflect for a full 8bit deviation and will be more obvious in signals involving MSB operation, it's hard to see how these static level errors can result in the displayed waveform.
After testing the effects of external loading on the two reference nodes, I determined that it was practical to regulate both nodes externally, using a shunt regulator. Because of their high impedance, it was even speculated, and later verified, that the two nodes could be shorted, as a single reference to both ADCs.
There was an LMV431AI floating around, which proved to like shunt regulating at 1V2393 to 1V2396 in the 50 to 100uA range. When located on the shorted dual reference node, regulation effects due to GUI screen positioning was reduced to below 1mV, and the undershoot/overshoot effects disappeared from the display.
Under worst case conditions - both channels set for midpoint in the GUI - shunt current totaled less than 380uA in the new regulator. Under these conditions the reference rose to 1V2404.
It was noted, however, that the DC base-line level had shifted upwards slightly in the GUI - something that could be expected if the reference voltage had reduced since the last DC Zero calibration.
Running through a DC Zero calibration routine seemed to take longer than was previously experienced. Shunt current in the new reference increased to 880uA levels during the procedure, suggesting that the unit was attempting to modulate the reference node, in order to produce a specific DC level in the display. Ominous. if so. This was a good time to go away and brew up a cup of coffee.....
The result - after approximately 15 minutes per channel and the receipt of an 'OK!' message - was a complete disaster. Depending upon where the zero line was set by hand on the GUI's display, for either channel, the waveform could be DC-shifted in the display randomly above or below the reference, being completely off-screen, in some cases.
So much for that idea. The effect was reversible when the new reference was removed and the two references were separated.
Note that during zero calibration, all these reference nodes appear to do is to march back and forth across the load regulation plots previously mentioned, in response to line positioning that simultaneously displayed in the GUI screen display.
When the external reference was present, The GUI displayed no movement.
Individually, the reference nodes react to external loading with a characteristic impedance of about 125R for 100uA static load changes. This is only slightly lower than the ~140R static impedance of the nodes measured when powered-down.
Any ideas as to why the zeroing is defeated by a fixed, slightly lower reference node voltage? What the hell are they trying to do?
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