LT Spice, Dflop:
I can set VHIGH = 5 and that works.
But if I add TRISE = 500p then VHIGH reverts to 1 volt.
And incidentally, what's the difference between Spice Line 1 and Spice Line 2? TRISE on either breaks VHIGH.
Building a pseurandom bit stream generator is too much work, but it's easy to clock random junk into a flop.
lørdag den 17. september 2022 kl. 23.45.50 UTC+2 skrev John Larkin:
works just fine,
Version 4 SHEET 1 880 680 WIRE 304 48 64 48 WIRE 64 160 64 48 WIRE 96 160 64 160 WIRE 96 208 -112 208 WIRE 304 208 304 48 WIRE 304 208 272 208 WIRE -112 240 -112 208 WIRE -112 400 -112 320 FLAG -112 400 0 SYMBOL Digital\\dflop 176 112 R0 WINDOW 3 156 69 Left 2 SYMATTR InstName A1 SYMATTR Value VHIGH=5,TRISE=10m SYMBOL voltage -112 224 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value SINE(2.5 2.5 10 0) TEXT -146 424 Left 2 !.tran 1
I tried commas, no help.
DFLOP is weird. I had rout=1m, and that messed it up. With rout=0.1, it's OK.
The flop output with trise=700p has a soft corner. A pulsed voltage source with the same specified rise time is sharp.
No surprise there. The bistable model is supposed to simulated a real part, and the pulsed voltage source is a mathematical abstraction.
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