Yup, that's about ideal.
Skew doesn't matter here, and daisy chaining is fine *if* everything is done right, which it wasn't in this case. ECL clocks are usually daisy-chained... many small chips and picosecond skew requirements between nearby chips. Star fanout to 50 or so loads gets messy.
We're leaning towards slowing down the edge at the xo, maybe with an R-C or an HC-class buffer, and adding a tiny-logic schmitt buffer at each fpga, giving most of a volt of noise immunity. There's no room for star traces, or at least not without a lot of ripups. If we put the tinies on the bottom, under the fpga's, they fit nicely and we don't have to waste a bunch of hundreds of bucks on a new solder-paste stencil and reprogramming the pick-and-place.
Hey, the CPU has a clock-out pin, same freq as the clock-in in this case. We could use *that* to drive the two following FPGAs in the string. It's a 68332, ancient process cmos, swings hard and makes nice sedate edges! May as well leave the deglitcher in there, so we don't have to re-release the designs.
John