That's about right. At high frequencies, synthesize a waveform (usually a sine) and lowpass filter it into a comparator. At low frequencies, just use the MSB of the phase accumulator as the clock. I think a glitchless transition can be made between those two modes.
And next step, do something trickier between the phase accumulator and the DAC, trapezoid maybe at a high DAC clock rate where the filter still helps.
A comparator makes a fast rise. The problem is at the DAC output.
Dithering sounds like a jitter generator. I'd rather put some clever waveform into the DAC.
It sounds messy to get extreme mag field stability. And a yig won't go down to 1 Hz.
Been done.
So resynchronise it it a good clock.
It doesn't have to. If you can tune the YIG oscillator over a continuous 2:1 range , a binary divider can get you almost literally any lower frequency - a thirty stage divider get you close to 1Hz. And the YIG oscillation frequency is a pretty accurate guide to the magnetic field - monitor that for feedback control of the magnetic field.
Although that is true if you set your zero crossing high/low by half a least significant bit (or half the smallest step in the sine wave table) then you can trade lower jitter for a small asymmetry in the waveform.
Then divide by two in the digital domain and you are done.
The other option is to integrate the output of the DAC so that you get a join the dots piecewise linear waveform much more amenable to comparator thresholding and interpolation in the time domain.
But then you have new problems - drift/offsets in the integrator, variable gain and delay offset as the frequency changes.
There is no free lunch!
If the purpose is to create a variable _timing_ generator (not just frequency generator), why mess with the DDS principle at all ?
Using a divide-by-N counter clocked at say, 1 GHz, you can timing intervals in 1 ns steps. With a 48 bit synchronous down counter, you can get timing intervals of several days with 1 ns timing steps. Some trickery is needed to avoid running all 48 stages at full ECL speed.
But the real question is, do you really need nanosecond step size in minutes, hours or day time scale ?
Admittedly, the 1 ns timing step is quite coarse at short pulses, inn which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS might be justified to get 1 ps timing steps. But for longer times, say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider after the DDS ? Combining the DDS and divide-by-N programming, quite strange periods can be obtained.
The DAC still increments once a millisecond.
The option is to do digital tricks in the FPGA. Almost free lunch.
I'm thinking that it's (barely) possible to simulate the DDS in LT Spice. The tricky part would then be measuring period jitter.
Most of our customers expect to set an internal trigger frequency. There are times when setting it to high resolution is valuable.
I can't do that in an FPGA. And resolution is mediocre around 10 MHz.
It might be interesting to program a 1 GHz SERDES channel (which we can do) DDS-sorta waveform that we can filter into a comparator. That's hard to think about, which I can delegate.
A straightforward DDS will have tons of period jitter at low frequencies, which is ugly. And some customers whine if we stop triggering while we reprogram a DDS (or a synth chip) and a divisor.
I'll ping the boys about the SERDES idea. That could be cool.
Peter Alfke probably could have. Sadly, he is dead.
So don't use a "straightforward DDS".
So ping-pong between two.
The last serial data link that I played with was the Taxichip back in 1988. It used an 8-bit to 10-bit recoding scheme to avoid sending troublesome bit patterns.
Working out what you were actually sending might be a bit tedious.
Cool, but it puts you right back at dealing with all the jitter issues of outputting the timing signal directly from the FPGA.
Numerical gain ahead of the DAC does help, though, as somebody pointed out upthread.
Cheers
Phil Hobbs
It's hard to do good work with a 10 bit DAC. A 16 bit DAC would improve the time step to about 16 us.
Wouldn't it be just as good (and symmetrical) to introduce a one-bit hysteresis? And not need to divide?
So, a first-order filter? What do you reckon a normal DDS filter is doing?
Clifford Heath
You just described a one-bit DDS. It doesn't need a lookup table, of course.
CH
make a square wave with the DAC, into integrator (filter) vary the amplitude
<snip>
Use a fast 8 bit down counter followed by a slow 40 bit down counter. If the fast counter is run at 1 GHz (1 ns), the slow counter only runs at 4 MHz. When the slow down counter reaches 0x0000000000, it can start reloading the preset value. At that time the fast counter is at
0xFF and it takes 256 ns before reaching zero and doing the preset. At that time the slow counter has already been reloaded and it can start counting as soon as the preset fast counter reaches 0 the next time. <snip>Then do not use DDS directly for very low frequencies.
Reprogramming DDS = loading a new addend value into the DDS. After that the phase accumulator increases more or less rapidly, so quite hard to even detect in a short time.
If you have a DDS for periods shorter than 1 s, you could add a divide-by-N for longer periods. Each time the divide-by-N reaches 0, you could enable the DDS addend loading, thus the timing would be quite clean, even for a time sweep. Of course, this will require precalculating the DDS addend and the divide-by-N before the divider expires, but a very primitive CPU could do it before a sweep or other predictable sequence.
Amusing. That wasn't exactly 'new' when I implemented it in 2002 or so. (
I used a crystal filter rather than a narrowband VCXO, but same difference.
-- john, KE5FX
Amazing documentation. Thanks.
Mike
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