The sawtooth defined by the MSBs of the phase accumulator isn't intrinsically band-limited but you know you can generate band-limited sawtooths directly in software, yeah? You just integrate a band-limited impulse train.
see e.g.
And your point is?
If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation.
Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not betting on it.
I am late into this discussion, so maybe missing something. The aim is to generate a programmed clock. Why not ditch the DDS and use a precision clock into a FPGA that digitally generates the clock
Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?
The concept of the DDS is to generate a sine wave, which would have some artifacts which could be smoothed by filtering, then a comparator would produce the square wave clock from the sine. This would allow very high resolution of timing, much finer than a cycle of the sample rate clock of the DAC.
However... when producing a sine wave that is much slower than the sample rate clock, the limited resolution of the sine value produces what is essentially a much slower sample rate and the filter doesn't work as well. This can be mitigated by using different filters to suit the output sine wave frequency.
I think the point is that John Larkin wants to generate an infinite number of arbitary frequencies, and can't afford to limit himself to dividing down even a very high frequency clock by a fixed divisor.
A DDS offers the option of using a DAC to interpolate between fixed divisors. The DAC produces a stair-case waveform approximating to a sine wave, so you have to low pass filter the DAC output so that the zero-crossings do happen between clock edges to get the effect you want.
John doesn't seem to have thought this through.
Ok, makes good sense. Thanks for the explanation. One could use delaylines to get sub cycle resolution, but I guess he must have discarded that solution
How would that work?
We want a user to be able to program a trigger rate from 15 MHz down to milliHz with high resolution and low period jitter. 1 mHz resolution is a reasonable goal. We can do that on some instruments now, but
Even the divisor is difficult if it's in an FPGA that has other stuff going on. Getting picosecond timing out of an FPGA has hazards, like crosstalk, ground bounce, and supply voltage sensitivity, which we measure in microvolts per picosecond.
So, I'm thinking about DDS clock synthesis from basics, and particularly thinking in time domain. It's basically a time domain problem, so there's nothing magic about sine waves.
This box does internal clock rate generation to mHz resolution, with an RF synthesizer (not a DDS) and post-dividers.
A precision clock, high frequency low jitter
Feeding into the FPGA with say 64bit counter, adding delay line for sub clock cycle accuracy
Compare and lookup on that counter, coupled to the delay line also
Like standard PWM done in microcontroller timer
Programming is cycle to cycle, changing just the compare capture word
Hazards can be dealt with the correct counter type, right?
Can you calibrate the FPGA?
Compare capture with delay line is purly digital, so should have no PDN issues pass through
This is not good for the fast clock rates, not sufficient resolution of the clock rate.
An NCO can be used directly for the slow clocking, since a clock cycle jitter is good enough. At faster clock rates, the sine lookup is added to the signal path with the attendant DAC and filtering. Actually, no reason to change the signal path in the two modes. The DAC will provide consistent drive and timing of the generated signal across the range. The filter will have nearly no impact on the slow clock.
Or... keep the same concept at all clock speeds and simply use different filters for different ranges. larkin keeps talking about how multiple samples go by with no change in the DAC value, but that's not actually a problem as long as the filter smooths the steps, same issue at any clock speed.
A hazard is a design failure. Use designers who know what they are doing. Crosstalk is not a significant issue with digital logic, again, as long as the designer is competent. Same for ground bounce, etc.
All timing issues with digital signals can be resolved by reclocking through your favorite FF outside of the FPGA. That can be as good as a DAC.
That's the tail end of the Shannon Sampling Theorem. A lowpasss filter can perfectly reconstruct a bandlimited waveform from periodic samples.
And not just a sine wave.
One could use a programmable delay to construct an arbitrary-frequency clock from a fixed-frequency clock, but then you have the problem of computing the delays and reprogramming them every clock.
I did play with that idea a little. The delay would in fact ramp, which works for a while.
That architecture works in theory, and the math isn't bad to do on-the-fly in an FPGA. One practical difficulty is building an instantly-programmable glitch-free delay line.
A second problem is that any output from an FPGA has picoseconds of excess jitter.
Or two DDSes and a mixer. ;)
Cheers
Phil Hobbs
Another approach, sort of like dithering or tape bias, would be to compute samples of
g = epsilon * sin(2*pi*N*f*t) + sin(2*pi*f*t)
and
h = epsilon * sin(2*pi*N*f*t)
for some suitably-chosen values of N(f) and epsilon,
and use a differential comparator.
Epsilon would depend fairly strongly on the CMR of the comparator.
Cheers
Phil Hobbs
you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine you want to turn that into a square wave so you stick it into a comparator.
The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc. At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s so 1uV tresh hold variation turns into a ~16us timing variation
ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop the peaks off since we are only interested in the zero crossing so 1uV tresh hold variation is now only a ~160ns timing variation
Or, just fine-tune a cavity oscillator by moving a wall, trombone-style. You get continuous frequency control, but it does need a moving part. Next step up from that, is a YIG system tuned with magnetic field.
Yig's are great, but you have to stabilize the current.
What you are missing is that when you appropriately filter the trapezoid, you get something back that is very much like the sine. If you don't filter, you have the stepped function, so clock periods of jitter. Might as well just produce the clock directly from the NCO. The other issues larkin is talking about can be mitigated by running the NCO output through a single, high quality FF external to the logic device.
Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC will change about every millisecond. And theoretically one step parks at zero volts. So jitter is bad. Gain doesn't improve things.
So if I have this right the DDS has lowest jitter at high frequencies and a digital clock will have lowest jitter at low frequencies, where you can calculate the optimal crossover frequency between the two for lowest jitter across a wide range, and you want to use the phase accumulator? of the DDS as your digital clock at lower frequencies, allowing for fast synchronized transition between the two? Been a long time since I used a DDS, not at all clear on the details, but is this basically what you are trying to do?
Glen
Oh, if your goal is to clock logic, gain certainly DOES improve things; you want the fast rise. And, 'one step' is exactly what the filter doesn't pass; your DAC is clocked at sub-microsecond intervals complete with some dither, and the microsecond-steps are filtered away. You're using the oversampling wrong if you have a millisecond duration zero volt output.
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