ECL helps as long as both outputs are equally loaded. For example, higher capacitance on one output can introduce switching transients. However, it is difficult to find differential sources. Double balanced mixers and XOR gates are single-ended. If you are trying to achieve high gain, small effects can add up.
I'm not so sure about cancellation. The propagation delay through the filter will change the phase. The group delay around cutoff of a butterworth filter can have enormous phase shift. High frequencies may even add instead of subtract.
The filter phase stays reasonably still, though, so the LO phase fluctuations remain highly coherent between the down- and up-conversions. 'T'ain't perfect, but it can really help sometimes.
I'm not sure I understand what you mean. The noise is symmetrical. It can add jitter to the zero crossings, but that's what noise does. You show this in your equation.
In the Griffiths approach, the limiting is done by back-to-back diodes.
There is no amplifier going in and out of clipping, so it's not clear how there can be a shift in the zero crossing.
Single-ended XOR gates are single-ended, but DBMs aren't necessarily. The RF and LO ports are both transformer-coupled, so you can drive them differentially with no issues. Even the LO port can be driven differentially for the upconversion.
It adds jitter to everything, including the time when the amplifier goes in and out of clipping. The filter applies a convolution to the entire waveform, not just the zero-crossings, so that shift is equally important.
The additive noise does the shifting, even if the rest of the hardware is noiseless. Diodes are not noiseless devices either.
Yes, the RF and LO ports are both transformer-coupled. So what difference does it make if these ports are driven single-ended vs differential? How does the transformer know how the input is driven?
That's the point. You claimed that DBMs were single-ended, and they aren't necessarily. So the fully differential approach is a good solution to the supply/ground coupling problem.
And single-ended drive means the drive current goes into the local ground plane and spreads from there to whatever decoupling there is, leaving a visible signal across ground plane inductance and resistance.
If he wants to waste his time on this after ignoring all the good advice so far then one of the cheap and nasty Chinese DDS signal generators that has a user defined waveform lookup table would be the way to go.
Nothing refutes a daft idea so effectively as practical experiment.
Not knowing exactly why he really wants to do this - the simplest waveforms that are steeper at the origin than sin(x) and matched in gradient at zero crossing are parabolic or more generally of the form
(1- (|x/pi-1/2|)^N)
(and that function negated that on alternate half cycles)
NB gradient of his triangle wave is 1 (or -1) everywhere but the gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). There is a very good reason why people generate sine waves by default.
I suppose triangle wave and diode shaping to a sine wave would be an option (HP once used it to very good effect and their patent for that network has probably long since expired by now). ICL8038 did a crude imitation of the same trick in their monolithic function generator chip.
The low pass filter needs to be frequency matched to the artefacts in the fundamental frequency being generated. No point in low pass filtering at 1MHz when the output is 10Hz. You need to attenuate the harmonics generated by the discrete steps in the DAC waveform.
A 1 MHz filter would be appropriate if the sample rate is well above 1 MSPS. But the resolution of the DAC needs to also support such a wide range of frequencies. If he only needs a low frequency output, then this is not a good solution. But he seems to be saying he needs the wide frequency range. In that case, it would seem obvious that multiple filters would useful. Just like they don't build radios to cover all bands without separate band select filters, there will not be a one size fits all solution here. Most of the ideas he has talked about will impact the jitter requirements. Unless he addresses the phase accumulator truncation, he's never going to get really good jitter, no matter how good the filtering is.
I don't recall the impact on jitter for a given resolution, but I found a reasonable phase truncation was 18 bits with an 18 bit sine table output. To improve beyond that with reasonable hardware (reasonable for my designs) requires sine approximation methods. But for his work, it would seem a CORDIC might be the right way to go. Add dithering to a few extra bits of sine with rounding, perhaps.
Thinking about possibilities is never a waste of time. It may lead to something useful now or later, and thinking is good exercise for thinking.
Try it.
The idea shooters here don't need experiments, when insults are easier.
And one has to do something about the fact that the DAC code will increment infrequently at 1 Hz. That is a time-domain concept.
I suggested digitally shaping the DAC waveform to increase the sample rate and slope at low frequencies. Or at all frequencies. Interpolation is one approach.
New idea: at some low frequency, just banging the dac rail-to-rail with the phase accumulator MSB will make less jitter than stubbornly insisting on making a slow sine into the filter+comparator. At high frequencies, the unfiltered MSB is a horror.
Oh, the refutation of an idea by an application of theory is just as effective as experiment, and multiple refutations of both sort have entered the discussion.
There are no 'idea shooters' more useless than those who keep up a chorus of 'why not' and ignore the sensible answers.
Yes, that's a good analysis. Transient analysis might tell you what a filter gives for a triangle wave or sawtooth, but the sinewave analysis of filter operation is much easier, and supports useful conclusions.
The DAC output has some wide band (thermal) white noise. If the wide noise power is close to the LSB size, do you need additional dithering?. At low frequencies, there is also the 1/f noise.
For audio frequencies "24 bit" 192 kHz DACs are available, which accepts 24 bit sample values, but in practice the last few LSB bits are buried in noise.
If you need better dither control, some DDS chips have phase and/or amplitude modulators built in, so the PM/AM inputs can be used to control the high frequency dither more precisely.
onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin:
ahh now I see what are on about, at very low frequencies the fixed jitter of a Fclk cycle could be better than a comparator trying to digitize a (noisy) slow rising sine
maybe a frequency dependent gain and clamp to maintain a constant slew-rate could work
The MSB of the phase accumulator has jitter of one clock p-p. The RMS jitter of that is 1 clock period / sqrt(12). That could be a few ns RMS jitter at mHz frequencies.
I was just thinking about possible tricks to reduce DDS period jitter at low frequencies, without the obvious post-comparator divisor.
onsdag den 10. august 2022 kl. 23.15.59 UTC+2 skrev John Larkin:
The sine and filter does that. Draw a line between the data points and see that the zero crossing doesn't fall on a clock edge
but it might help to gain up the sine to increase the slew rate so it doesn't hang around the comparator threshold forever, when all it has to do is delay a variable +/-1 cycle
larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.
He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter.
The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.
I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates.
afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.