DDS questions

That's actually a good way to visualize the problem. You don't care about the peak, you care about the zero crossings. At frequencies where the LSBs toggle less often, the resulting phase error will corrupt the zero crossing points at low offset frequencies. You can't fix this with a filter, only with a DAC.

Try it and you'll see (as I did, back when the HI5731 DAC was the SotA and I didn't have one in the parts drawer.) The ugliness of the output that you will get from the MSB by itself is hard to exaggerate.

-- john, KE5FX

Anywhere near Nyquist, the DAC output is ghastly. It looks like random noise, hard to see anything coherent on a scope. But after a good filter, it becomes a beautiful sine wave.

If you flip the impulse response of a lowpass filter (like doing convolution) it shows how much the filter remembers, how much it looks back in time. My proposed sawtooth has a sharp jump that a sine wave doesn't. If the filter has forgotten the jump, the sawtooth is ideal. If not, the soft history of a sine wave might be better.

But, doesn't the 'sharp jump' have synchrony with a clock edge? And, doesn't a sharp jump, like a clock, require a big impulse of current out of your filtered power supply? The sinewave is cleaner to drive, and less insistent on knowledge of dispersion in the dielectric materials. As others have pointed out, that's why wiring time delays are precise only with sinewaves: no hook there.

Sure. The dds DAC is clocked by the main clock. Every dac output point is clocked.

We are in the picosecond timing business. We use sub-ns edges for clocks and events. We don't use sine waves!

Making the trapezoid from the NCO output is not the same as making a sine wave and filtering. The "logical end" of that is actually generating a square wave with all the attendant jitter. So the trapezoid would increase the jitter and be harder to filter than the sine wave.

You must have enough phase bits to prevent phase noise since this produces, hard to filter (meaning impossible) close in spurs.

Yup. Is there some reason you can't piggy back on the SPI protocol to add bits to control your octave divider?

Around here, picosecond-level errors mean that somebody (i.e., me) is going to have a bad day at the (proverbial) office. :)

-- john, KE5FX

The power supply isn't an issue. All sorts of things are whacking the power supply.

But if we make a sawtooth that ramps from -V to +V, and we filter that, the big negative spike happens at the input clock rate, so wobbles the zero crossing and makes jitter. The filter isn't perfect so doesn't forget the big negative step in half the sawtooth time.

So move the comparator trigger level up, to 0.9V instead of zero, and that gives the filter almost twice the time to forget.

We swept two edges across one another and poked them into the data and clock of an NB7V52 GigaComm flipflop.

We saw about 60 fS RMS jitter, which is the flop and the circuits that generated the time sweep.

Common DDS evaluation boards come with a 7th-order filter at about 40% of the clock rate, so for a 180MHz AD9851 at 180MHz the filter is around

72MHz. That produces reasonable signals between 30-70Mhz, but if you want to produce 1MHz, the signal turns into a staircase roughly following the sine curve. (the 40% is a compromise to allow the filter to remove most of the first DDS image, which will be at 60%)

If they started with a triangle wave (as you can get from a cheap AD9834 for example) it would still be a staircased triangle - the filter softens the staircase steps but doesn't do anything to make the signal look like a sine wave. You'd need a different filer for that.

Clifford Heath

A post-filter sinewave's zero crossings are NOT clocked, though, so can be asynchronous. The 'filter' has a Q of maybe 100, gives the sinewave's stability a couple of extra digits worth of jitter suppression. Such a filter, with a transient rather than a single-frequency drive, depends on response over ALL the harmonics that make up that slope. Self-resonance of inductors makes the high harmonics hard to predict (and other broadband component issues apply to other cases).

Folk with serious timing issues can use LC filters with superconductors... and regulate the tank temperature with helium boiloff pressure gages.

The filter adds back in some of what you would have got by increasing the number of MSBs fed to a sine lookup table (and more amplitude steps, maybe).

Two adjacent zero-crossings will occur at a different time in the filter output compared to its input, unless the clock is a harmonic of your output frequency.

You don't want the filter to forget. The point of the filter is to integrate the timing, average to put it another way. You want it to remember the zero crossings so as to remove as much jitter as possible. You keep talking like what is important is only the careful construction of the current edge of the waveform.

I suspect the minimum will vary depending on the criteria. You don't gain much by making the filters so narrow that their parametric drifts start going all over the place. Lots of things get worse by factors of Q.

Cheers

Phil Hobbs

I never bought into the Collins theory. A bit of fiddling in LTspice and simple pen-and-paper work shows the last stage is all that matters.

Other attempts to improve on Collins fail in the first paragraphs. For example, Attila Kinali assumes the limiter has hysteresis. As far as I know, no limiter worth it's salt has hysteresis. See

It is referenced in

snipped-for-privacy@lists.febo.com/msg08534.html

One problem with high gain limiters is ground bounce. This can cause feedback to the input stage that causes effects similar to hysteresis, or even oscillations. Many limiters restrict the minimum slew rate, or even do not specify the performance in a band around zero. This means the circuit cannot be used at low frequencies or even DC.

I believe it was Bruce Griffiths who championed low gain stages driving back-to-back diodes between stages. This would alleviate the ground bounce problem and allow slew rates down to DC.

Just using fully differential stages (a la ECL) fixes the ground bounce problem pretty well.

The wideband noise both adds and intermodulates with the desired signal, causing phase noise. In the high-SNR limit, the RMS phase noise deviation (rad/sqrt(Hz)) due to additive noise can be found from the small-angle approximation:

<delta phi> = 1/sqrt(2 * SNR ).

As long as the intermodulation is small, I agree that the last stage is most of what matters, but not 100%.

Noise intermodulation will shift not just the zero crossings, but also the times when the amplifier goes in and out of clipping. The next filter will turn that into a zero-crossing shift.

Cheers

Phil Hobbs

I should add that it's important that the limiter be fully differential, because otherwise you get a bunch of AM-PM conversion.

It's also quite feasible to mix down, limit, filter, and mix back up again. With ideal mixers, this reduces the limiter's phase noise power by a factor

(f_RF/f_IF)**2.

The LO doesn't have to be as stable as the desired signal, because its phase gets subtracted and then added again.

Cheers

Phil Hobbs

It is an optimum in that it is most easily filtered to give lowest jitter.

He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution.

Anyone who wishes to research DDS design will find this.

Maybe. But it's worth thinking about. The optimum DDS waveform is entangled with the filter response. The sawtooth is interesting. It could be Spiced, in some number of hours. Or days.

We can design the schematic and do a board layout and futz with DDS shapes and filters and dividers later.

It would run at the XO rate of course, but one might generate a very slow trigger rate by doing something smarter that generating a very slow sine wave. A 1 Hz synthesized sine wave, filtered and stuffed into a comparator, is going to have a lot of jitter.

Just thinking. That's often not popular.