Tschaggelar
stages.
I'd have to do some digging, but there is a classic equation that relates the speed of the comparator to the number of stages. Generally more stages are faster if you are using the comparator in its "linear" region, i.e. close to zero volts. It is not a situation where you are propagating logic, but rather you have a number of stages moving linearly a the same time, each one amplifying the other. If you want more bandwidth, you use less gain per stage, but more stages. This way written up generally in strobed comparator design, when you off-set cancel each comparator stage in one phase, then compare in the next clock phase.
Of course, now I made a fine mess for myself since I need to dig a reference on this.