cmos 74hc debounce pull up resistors

I assume you're using two cross-coupled NAND gates to debounce the SPDT switch.

Yes, you need two pull-up resistors-- one for each input-- to make the input high when the switch contact is open.

Well... if you look at the leakage current specs on the gate input you'll get an upper bound on the resistor value. Eg.

Ii = +/- 1000nA (max over temperature), so for 4.5V supply we should have no more than 1.35V drop accross the resistor, so Rmax =

1.35V/1E-6 = 1.35M ohms, so say 1M. Higher if you like to live dangerously (typically, at room temperature, with no PCB leakage, 10,000 times higher will work, so even 10M is pretty safe in many situations).

But if you don't care much about power consumption, a value like 4K7 or 10K will result in a circuit that may be less sensitive to electrical noise, and may work more reliably with whatever switch you have.

Best regards, Spehro Pefhany

--
"it\'s the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com

Do this and you have crackling sharp debounced switching, zero current through the resistors, and a calculation-free process capable of handling a SPDT or (ON)-OFF-(ON)... View in a fixed-width font such as Courier.

. . . . . . .---+-----------------------. . | | | . | | __ | . [10k] '-| \\ __ | . | | o-+---------| \\ | . +-----|__/ | | o-' . | '-[10k]-+-|__/ . | | . o-----' | . .--o-- | . | o-------------------------' . | . --- . /// . . . . . . . .

Looks interesting. I can see how the resistor would only be accross both rails for a short time spike, otherwise it would be neutral, with a logic 0 (or logic 1) on both sides of the resistor while the switch is stable. This avoids the static pull-up resistor from pulling current on the leg which is grounded. I will try to run this through SPICE to see how well it works. (you don't happen to have a spice model for this handy?) Thanks, Ron

If static discharge through the switch is your main concern then you can select a switch designed for this purpose, the vast majority of panel mount small signal stuff intended for applications like this protect against ridiculously large static voltage discharge making it onto the switch circuit terminals; that is just the first line of defense, the HC family will take care of the non-existent residuals. And, nope, did not run it through SPICE.

If you want to be beastly about it, use cross-coupled inverters and forget the resistors entirely. Best regards, Spehro Pefhany

--
"it\'s the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com

LOL- heck why not...

I think that low-power consumption is more important to me. I think the short spike in current will not be a problem, since the nand gates will flip-flop to match the input state of the switch very quickly. I was more concerned about some of the other more common circuits where you have a resistor between Vcc and Gnd which is constantly draining power. Your solution only has a very short spike but then it's neutral and shouldn't have any current through the resistor, as long as the gate output is at the rail voltage. Ron

This is even more fun:

John

I think ill stick to the SR FF with the resistors between ground and the output pins... Looks like im good to go. Thanks for all the help. Ron

"John Larkin...

I prefer not to have floating antenna's in steady state. Also, the next circuit (uses a non-inverting buffer) saves on wiring, and with multiple switches you can wire most contacts in parallel:

|\\ + ------o | \\ ---o--------| }--------------- GND ------o | | / | | |/ | |_________|

Arie de Muynck

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These take less wire: ;)


          Vcc

Flawed idea, susceptible to causing metastability at the receiver...

Yup, that's a nice one. And a cap to ground would harden it against stiff transient noise spikes, if present.

John

"Fred Bloggs" ...

I did measure the bounce time and pattern of a lot of different switches and relay contacts. Never saw any "first contact" below 100ns. That's enough to settle even a good old CD4000 buffer. Do you have you any data on the contrary?

The circuit never failed me, even when using it to edge-trigger FF's or counters.

Arie

Didn't you mean something like....

|\ |\ + ------o | \ | \ ---o-----+--| }0---| }0--+--- GND ------o | | / | / | | |/ |/ | | | +---\/\/\/\/------+

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |

"Jim Thompson" ...

I have used several variations on the theme, including this one. The very first version was with a 1/6th CD4050 buffer on 5V, and I had little space (no SMD resistors back then). It is AFAIR about 20mA sink, 10 ma source when shortcircuited against the rails. That current only lasts for Tpd, about

100...200 ns. So that one was exactly like my diagram.

I would have used 470 Ohms and 2/6 SN7404 (or SN7414) for TTL, etc. because of the higher sink current. Or nowadays a tiny-gate '125 (with an SMD resistor, I lost some wild hairs and the resistors their size).

Arie