I am looking to use a SPDT switch (center GND) with the NO and NC contacts wired to the inputs of a 74HC00 CMOS NAND gates. Is it necessary to tie both (NO and NC) inputs to power through a pull- up resistor? I have seen this done on TTL circuits, but I thought that the inputs on the CMOS had such high resistance that it would not be necessary. Yet, I also read in many places that the inputs of a 74HC cannot be left floating. So im going to assume they need a pull-up resistor. Is there any way to figure what the proper resistor value should be to ensure the input is not in the invalid-zone between a logic 0 and logic 1 on the input? Is this done simply by computing the desired voltage drop accross the resistor? If so, the voltage drop would be very small and the resistor would have a very low value, but this would lead to high current draw on the input pin which is grounded through the switch... What's a good value for a pull-up on a 74hc part?
15 years ago