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Consider a snap shot of a small part of the turn off process in the case of the FET going to ground:
Cgd Rx Gate swing ---!!--+----/\\/\\/---+-- Vout ! ! \\ ! / Rds --- External \\ --- Capacitor ! ! GND GND
The gate is swinging down and the Rds value is about to start increasing. If we assume a constant current in Cgd and a huge external capacitor, we can say that the current splits between the two paths in the ratio of the resistances.
At each instant in time, Rds has some value. As time goes by, the Rds value is increasing. When the Rds value becomes more than the Rx, most of the current will start to charge the capacitor. If the Rx value is very small, more of the charge ends up in the capacitor than if it is larger.
In the sample and hold case, the GND end of Rds is driven by a low impedance voltage source but the added resistor's function remains the same.