Best bang-for-buck uC

My low cost favorite is STM32F030F4, 16 kB program flash, 4kB RAM,

11 ADC channels, 5 timers/counters with 10 hardware PWM outputs, USART, SPI, I2C, DMA channels, 48 MHz clock, works from 2.4 to 3.6V.

Definitely STM32F030F4 is more powerful than ATTiny85. At Mouser STM32F030F4 is sligtly more expensive than ATTiny85 for 1 piece (1.16 Euro versus 0.986 Euro), but cheaper for

100 pieces (0.757 versus 0.823). For 10 you get exactly the same price, for 25 ATTiny85 goes to lower price break (0.91 Euro) while STM32F030F4 stays in the same price break up to 100.

At Farnell STM32F030F4 is cheaper for any quantity. Chinese sellers sell 10 pieces of STM32F030F4 for 4.4 dollars including shipping. STM adverties that you can get on for 25 cents (presumably when you need milions). So price depends where and how much you buy, but for me STM32F030F4 is cheaper.

--
                              Waldek Hebisch

I don't know either. The free Forth tools tend not to have debuggers as Forth lends itself well to debugger free development. But any language can be used with Eclipse if I am not mistaken. So then you have a debugger.

Not sure what you mean about supporting the "range" of 8051s. If the 8051 doesn't use the same code, it really isn't an 8051.

Your use of the terms "brain-dead" and "outdated" shows you have an emotional connection to this decision. These are not engineering terms. You know little about the CPU but are rejecting it for not having the image you want from your CPUs. The only issue is whether the device meets the requirements of the project. As has been stated, the 8051 is the only CPU that can meet certain project requirements that some users have.

--

Rick C 

Viewed the eclipse at Wintercrest Farms, 
on the centerline of totality since 1998

You can certainly use Eclipse for editing any language (at least, anything written in plain ASCII. APL probably needs an extension), and there are plugins for language syntax highlighting and other tools for lots of languages (again, I don't know about Forth). But that does /not/ mean you can debug the language - that requires support for the language in the debugger. Eclipse can act as an interface to gdb, and gdb supports a number of languages (assembly, C, C++, Fortran, Go, Rust, Ada, etc.). Other languages like Python are also supported with the right plugins.

There are lots of variants of the 8051, with different types and sizes of memory, extra registers, extra instructions, etc. They share a common core ISA, but there are lots of details that are important if you want to have efficient code.

It is not emotional - I just don't like them! ("outdated" is factual, "brain-dead" is opinion.)

I know more than enough about 8051's to dislike them and to reject them given the choice. The decision is based on fact as well as personal preference. I /have/ used them occasionally - because sometimes I am /not/ given the choice.

No, that is not the only issue. It is certainly an important issue - it is a requirement, obviously. But once you have established that a project can be handled by microcontrollers A, B and C, then you have to choose between them. Many factors come into play, including price, power, availability, ease of development, flexibility - different weightings will be used for different projects. 8051 cores score low on all of these. So, as I said, given the choice I would generally pick something other than an 8051. (If the choice was 8051, COP8 or PIC16, it would be a harder decision.)

In which case there would be no /choice/. That is what "choice" means!

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I know this is an old thread, but I came across it when looking for somethi ng else and had a few brain cells wakened.

The difference between the GA144 and any other processor is not the way the processors are connected so much or nearly any other aspect that folks foc us on when learning about it, the real difference is not the various strong points it is the weakness of only having 64 words of RAM, which is combine d data and program space, on each processor. So programs have to be small, (but it does have 5 bit instructions, so up to 4 per word) so small you sh ouldn't think of them as programs anymore. The GA144 core processor (the F

18A) is a bit of programmable logic that is not configured with individual bits, rather with instruction streams.

I have not designed any apps for this CPU myself other than paper studies t o see what will fit. But in the Forth language the user is encouraged to w rite in a very modular fashion with a lot of nesting. I think software des ign on the GA144 would need to do the same thing, consider the F18A as an e lement on which to implement a few words and structure them in a hierarchy to accomplish a task.

Rick C.

Not directly related to this issues, but some recollections of articles in electronic journals from the early 1970's.

In one article it was speculated that one day in the far future the processor clock speed would be over 1 GHz and calculating sin/cos etc. would be hyper fast. Apparently the editor assumed that those functions were calculated using Taylor series. The article suggested using the trigonometric equation

sin(a+b) = sin(a)cos(b) + cos(a)sin(b)

and doing sin(a) and cos(a) with table lookup.

With sufficient small steps cos(b)=1 and sin(b) = b/2pi. In reality, the trigonometrical functions in those days were calculated using 3rd or 4th order polynomials for single precession, so not much advantage. In an other article an Intel representative was interviewed what happens, when it is possible to integrate a million transistors on a single chip. He could not give a clear answer.

My guess is that the situation today is similar with 1000 or a million processor cores available.

The CORDIC algorithm was invented in 1956.

Two decades later implementing floating point plus CORDIC on a 6800 was my first paid job as a vacation student. I still have the code :)

CORDIC was also easily implementable in hardware.

On the Sinclair Scientific calculator, maybe.

As always, the hardware is easy, but programming techniques for multiprocessor systems are still in their infancy.

The *only* processors that have a decent hardware+software story are the XMOS xCORE processors with xC. They have been around in several generations for over a decade, and are

*very* usable for *hard* realtime applications.

The xC+xCORE has a good pedigree: the key concepts have been around since the 70s (xC/CSP) and 80s (xCORE/Treansputer).

Certainly the solution space has not been adequately explored. I wonder if some sort of neural net would be practical if you could dedicate a processor to each neuron? You could simulate a very fast thinking cockroach with 1000 nodes.

Rick C.

Oh, yeah, you are *that* guy. Yes, we've had this discussion before. They are good for a small class of applications which they are optimized for. Otherwise the advantages of other processors or even FPGAs make them more suitable.

I was just browsing FPGA prices and I can get a small FPGA for $2.50 qty 1. Unfortunately volume FPGA prices are seldom advertised, so hard to tell what the 1000 piece price would be.

Rick C.

Obviously.

But I haven't seen *any* application of the GA144 you mentioned. As for the 1000 processors chips, I have seen zero implementations, zero programming techniques and zero applications for them. The XMOS devices are therefore (currently) infinitely superior.

Of those, the programming techniques are the most difficult; get those right and implementations and applications may

*follow*.

I strongly suspect that anything with 1000s of processors will have no significant advantages over an FPGA.

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Yes, the GA144 was designed as an experiment rather than with any applicati on in mind. However, I'm told they have customers, one application in part icular was for an advanced hearing aid using something much more advanced t han a graphic equalizer type of filter. Seems the original prototype requi red the use of a pair of TMS320C6xxx devices which use around a watt each i f I remember correctly. This type of signal processing app has potential f or a multiprocessor with little memory, as long as it doesn't get too compl ex or if it needs external memory the bandwidth isn't too high.

I don't see that. The super computers of today use standard processors, no t FPGAs. "Tianhee-2 uses over 3 million Intel Xeon E5-2692v2 12C cores", a lthough that is yesterday's fastest computer surpassed by "The Sunway Taihu Light uses a total of 40,960 Chinese-designed SW26010 manycore 64-bit RISC processors based on the Sunway architecture.[6] Each processor chip contain s 256 processing cores, and an additional four auxiliary cores for system m anagement (also RISC cores, just more fully featured) for a total of 10,649 ,600 CPU cores across the entire system." This monster uses 15 MW... yes,

15 MW! A professor in college used to kid about throwing the power switch on his CPUMOB machine and watching the lights dim in College Park. The Sun way would do it for sure!

A new machine is due out any time now running at 130 PFLOPS. Called the AI Bridging Cloud Infrastructure, "The system will consist of 1,088 Primergy CX2570 M4 servers, mounted in Fujitsu's Primergy CX400 M4 multi-node server s, with each server featuring components such as two Intel Xeon Gold proces sor CPUs, four NVIDIA Tesla V100 GPU computing cards, and Intel SSD DC P460

0 storage." Expected power consumption will be down to only 3 MW.

Rick C.

I was assuming comparing FPGAs with something /vaguely/ similar to the GA144, or that Sony cell processor, or that intel experiment with 80 cores on a chip.

Comparing something that, as I intended, fitted on a large PCB and plus into the mains with something that fits on a tennis court and plugs into a substation isn't really very enlightening.

There's a fundamental problem with parallel computing without shared memory[1]: choosing the granularity of parallelism. Too small and the comms costs dominate, too large and you have to copy too much context and wait a long time for other computations to complete.

That has been an unsolved problem since the 1960s, except for applications that are known as "embarrassingly parallel". Canonical examples of embarrassingly parallel computations are monte carlo simulations, telecom/financial systems, some place/route algorithms, some simulated annealing algorithms.

Cache coherence traffic grows faster than the number of cores, and eventually dominates unless you go to a NUMA architecture.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

Oh, indeed, that is inherently non-scalable, with /any/ memory architecture. Sure people have pushed the limit back a bit, but not cleanly.

The fundamental problem is that low-level softies would like to think that they are still programming PDP11s in K&R C. They aren't, and there are an appalling number of poorly understood band-aids in modern C that attempt to preserve that illusion. (And may preserve it if you get all the incantations for your compiler+version exactly right)

The sooner the flat-memory-space single-instruction- at-a-time mirage is superseded, the better. Currently the best option, according to the HPC mob that traditionally push all computational boundaries, is message-passing. But that is poorly supported by C.

For an amusing speed-read, have a look at "C Is Not a Low-level Language. Your computer is not a fast PDP-11."

It has examples of where people in the trenches don't understand what's going on. For example: "A 2015 survey of C programmers, compiler writers, and standards committee members raised several issues about the comprehensibility of C. For example, C permits an implementation to insert padding into structures (but not into arrays) to ensure that all fields have a useful alignment for the target. If you zero a structure and then set some of the fields, will the padding bits all be zero? According to the results of the survey, 36 percent were sure that they would be, and 29 percent didn't know. Depending on the compiler (and optimization level), it may or may not be.

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Your explanation is not of value. The GA144 is a very odd duck, but the ob jections most people have with it are pointless. They complain you can't u tilize the full MIPS available in the processors because of the limitations ... so? A chip isn't about one number. It's about getting a job done. Yo ur hand waving above is not at all useful when considering FPGAs to multico re processors. So what is different between the two in the way you analyze above?

None of this is useful in comparing FPGAs to multiprocessors.

Rick C.

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Not if you don't use cache.

Rick C.

Fun. He's a CS academic, so he probably doesn't write programs and so doesn't realize how much stuff can't reasonably be done in his favourite toy language, but it's a good read anyhow.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

It's got nothing to do with you, it's the processor architecture. If you want global cache coherence in a highly multicore processor, it has to be architected to support that. If you do your own custom CPU in FPGA, you can do whatever you want, but general purpose means general purpose.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

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Of course the NXP LPC802M001 is a 32-bit chip with 12 12-bit ADC channels, 16k of flash, 2k of RAM, 3 PWM outputs, all for 58 cents in thousands.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com