Best bang-for-buck uC

AFAIK, GPU cores are vector units: an instruction decoder unit follows the program, directing N register files and ALUs and memory buses to do the operations en masse.

And so there are two kinds of cores: the ALU parts, and the instruction parts that control them. I forget which kind is which, when you're shopping for GPUs -- I thought it's that, CUDA cores (to use NVidia for example) are the ALU parts, and there's another term for the top level sets-of-cores parts.

So there are some problems that can be computed very easily with these: anything where the same operation is performed upon huge swaths of data, of course, are fine (linear algebra). Less so if you have, say, loops per pixel, like ray tracing, or, rendering a fractal. There are some tricks you can do, like using arithmetic as conditionals (instead of "(condition) ? (expr1) : (expr2)", you use "(condition == 0) * (expr1) + (condition != 0) * (expr2)"). But anything that requires branching/looping, per element, that can't be optimized this way, is right out.

In contrast, a pile of general purpose compute cores, that do allow branching per element, could solve that kind of problem quickly.

Tim

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Tim Williams
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I was scared of C++ for a while, too. With time and patience I learned to overcome these fears. With modern compilers the modern dialects are good performers, even on the AVR 8 bit architecture. It ain't your grandad's 8 bit!

Reply to
bitrex

"Raymarching" is the trivially-parallelize-able version of raycasting:

Can't easily do multiple reflections, though, as that would require the aforementioned loops-per-pixel.

Reply to
bitrex

Tim Williams wrote on 8/26/2017 3:16 PM:

This particular chip has some serious limitations like memory size. It is a challenge to use for any complex task. $/MIPS is not a particularly useful metric.

None of those things seem to apply to the GA144, so not so general, at least not the way you stated it.

Yes, that is how I view these things, as a FPPA (Field Programmable Processor Array) rather than an FPGA.

Yup!

The GA144 only connects in a square grid to the local cores. So only the outer CPUs have access to any IO pins and any other core has to talk through those. People get their knickers in a twist focusing on the "loss" of MIPS from handling message traffic, but rather than focus on the one resource which is *not* in short supply, the focus should be on making it work to solve a given problem.

This may have some utility, but I think it is a bit off the mark for the GA144, too high level.

Yes, definitely too high level without there being someway to apply this to the GA144.

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rickman

OTOH, your software development would cost much more than the saving obtained from buying the more demanding, barely fitting, hence "cheaper" part. So, if you are not interested in high volume production anyway, why does the cost of the parts matter? They are peanuts compared to the NRE costs.

Best regards, Piotr

Reply to
Piotr Wyderski

He's just like that. He will build in qty of 100 or less and sell a total of say 500 units, but is very concerned about unit price. I get it. It's a bit of an emotional thing to want to optimize your unit profit, even if not always logical.

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Rick C 

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rickman

Playing devil's advocate, this kind of "cost optimization" is pretty hard to unlearn. It is somehow imprinted in the back of the head. Logic does not always come first. I have seen this in at least two other cases where professional electornics designers insisted on using a semi-obsolete, but dirt-cheap parts where a modern, but more expensive IC could handle the issue hands down. The total quantity was 5...

Best regards, Piotr

Reply to
Piotr Wyderski

That's exactly what PSOCs do. The CPU is called UDB in their parlance and is composed of a simple 8-bit core + two FIFOs for easy DMA integration + 8 FPGA-like LUTs. They also can be joined to form 16-, 24- and 32-bit units. You have 24 of them. A nice balance of Verilog and C than in the case of FPGAs + true 5V capability, not just tolerance. Good option for smaller projects, where the initial FPGA system complexity of ~5 ICs (the FPGA itself, config ROM, data ROM, data RAM and ADC) might be an issue.

Best regards, Piotr

Reply to
Piotr Wyderski

I guess I thought that was the point I was making? For my own small-volume stuff it doesn't make any sense for me to be trying to squeeze out pennies hunting for a different uC for every project. If I need an 8 pin just keep one variety of 8 pin in stock that's a great all-rounder with a lot of nice features and has a good toolchain, and have some known-good boilerplate code for that device that ideally can be re-used. One project might use 1k of flash and not use most of the peripherals, another 6k and more of them, but there's not much point in trying to save pennies by looking for a cheaper device with less RAM for the former project.

IMO the ATTiny85 gives you a lot of re-use flexibility for different projects for not that much extra compared to the more humble uCs, but without having to step up to a device with more pins or a more sophisticated core architecture.

Reply to
bitrex

Nah, the point I was trying to make (maybe didn't come out right) is that the '85 is a great all-rounder that is a little more expensive than the garbage-tier, but that's OK for many folks who don't make in big quantity as having a nice toolchain and a luxurious amount of program memory for a few pennies more is great. ~95 cents for 8K vs ~60 cents for 1 or 2k is a big jump for pennies that aren't worth worrying about in quantities of hundreds.

Reply to
bitrex

...

Oh, well, getting rid of memory entirely* would obviate that.

*So to speak. Nearly. I guess.

Oh, a mesh computer, why didn't you say so!

Not so bad when you've got so many to spare: example, dedicate a few rows of cores as data routing (which can be any combination you like: duplexed, synchronous, packetized, variable length, addressed...), and use the remaining perimeter as your parallel processor. You might still get dozens of cores in parallel that way, even if the utilization is effectively maybe

20%.

But that wouldn't be very useful without a compiler to handle it for you. Maybe not down to creating the messaging structure automatically, but there could be a library of options at least, and perhaps within a suitable framework, it could be able to choose, or recommend, the most suitable methods.

Yeah, the problem is the thing getting popular enough (or into a research project), where enough smart people have the time to study the system, and create those frameworks.

It would also be nice if the frameworks are flexible, and if they're based on the broader range of parallel processor architectures out there, which would require studying the literature as well as the marketplace. Millions of dollars of research, easily...

Tim

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Reply to
Tim Williams

ly the

Shades of the Transputer. Does it have an Occam compiler?

Cheers

Phil Hobbs

Reply to
pcdhobbs

Each core can "know" what the load is for the cores on its perimeter; if some core needs to send a message to the perimeter a best-first/greedy-search algorithm like beam search might be able to be used to find the path where passing would cause the least disruption.

Reply to
bitrex

And are these 8051 Forth tools free, full-featured, and do they generate efficient compiled code? Do they have modern IDE's and debuggers? Do they support the huge range of 8051 variations with different memory types, double accumulators, extensions, etc.?

I don't know the answer here, I am just asking.

SDCC is a reasonable C compiler for the 8051, and is entirely free. It does not generate as tight code as the massively expensive ones, but it is (apparently) OK. My experience with "top-class" 8051 C compilers has been poor - the code may be efficient, but the C compliance has been bad.

Given the choice, I would never choose to use an 8051 core - or any similarly brain-dead and outdated ISA. That would apply even if I were programming in Forth or assembly - there are so many good ISA's around, that it makes no sense to pick such a bad one unless the choice of peripherals on the microcontroller are overwhelming.

Reply to
David Brown

"Bang for buck" is about maximising processing power per dollar spent. "Bang for /a/ buck" would be about maximising the processing power within a one dollar budget. It is a different question.

It is possible that this was the OP's intended question (I haven't read all the replies in this thread yet). And it is arguably a more interesting question. But as far as I read the post, it is not what was asked.

Reply to
David Brown

The software development tools for the msp430 are free (the good ones are, anyway), and the debuggers are dirt cheap.

Of course you are right that unit cost on parts is usually of little relevance unless the volumes are high. Even if the development tools are free, development /time/ is not, nor are things like designing and producing the PCB's.

Reply to
David Brown

The huge advantage of the AVR/ARM architectures is the free-as-in-free and free-as-in-beer availability of efficient, regularly-maintained HLL compilers with excellent compliance to the language standards, e.g. the GNU AVR and ARM embedded toolchains.

Reply to
bitrex

Not just raw processing power but also flexibility and ease-of-use

Reply to
bitrex

I fully agree.

Another reason is that those architectures are ones for which such toolchains can be made. You can't make such a C or C++ toolchain for the 8051 and that class of cpu core. (The absence of such toolchains, despite the widespread use of the 8051, bears witness to that. SDCC is an impressive project, but not of the class of gcc.)

Reply to
David Brown

But did you mean you wanted to know about the best device for under $1, or did you want the best value for money regardless of budget?

Either way, of course, a specific recommendation needs more detailed requirements.

Reply to
David Brown

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