Battery simulator design

I'm thinking of building myself a (one-off) battery simulator to test some LiIon charging ICs I'm using. The "battery's" voltage would be between, say,

-- Totem-pole output: 5V bus to P-channel FET to "Vbat" terminal, Vbat to N-channel FET to ground

-- Error amplifier compares battery's setpoint voltage (adjusted by a pot) to the Vbat terminal

-- If Vset - Vbat > 0, I need to souce current -- take the error voltage, compute 5V-Verr with an op-amp, feed to P-channel FET's gate

-- If Vset - Vbat < 0, I need to sink current -- invert the error voltage, feed to N-channel FET's gate

So effectively then are two control loops (one for each FET), both being run off the same error amplifier output.

Does this sound reasonable? Is there an even simpler strategy?

Thanks,

---Joel