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Are 8255s operating at 3.3V available?

Hello,

I am designing a SoC based system where I need to interface an 8255 PPI with an ARM based CPU. I am using memory mapped I/O for the interface. The problem is the data bus pads of the SoC chip is not 5V tolerant. It can tolerate a 3.6V max logic level swing on its data bus pads. I dont want to use a level shifter circuitry because of cost issues.

Has anyone used an 8255 which can operate at 3.3V ? Is such a device even available? Or could some one suggest some other chips which can provide the functionality similar to 8255 but can work at 3.3V?

Thanks in advance!!!

Rgds, VSP

Reply to
VSP
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The 82C55's I've used all require 4.5-5.5V, but I suppose that doesn't mean someone else might not know of one that works at 3.3V. I'm just not aware of one.

What kind of timing do you require? Can you specify the set up and hold times for your memory interface to the chip, etc? The usual

82C55 requires some 150ns or 250ns for the /RD pulse width, and so on... are you able to meet these timings? More? Less? Do you need all 24 I/Os? More? Less? Is the 44PLCC packaging usually found for an 82C55 okay? Have you searched Maxim or Microchip for their port expanders? Would SPI or other serial interface be okay?

What have you considered and rejected?

Jon

Reply to
Jonathan Kirwan

Hello Jonathan,

I need to interface a SLIC & Audio Codec to implement a VoIP based system.The SoC chip doesnt provide enough GPIO pins to interface with the SLIC/Codec hence I am forced to use a 8255 to increase the GPIOs of the chip.

Since this interface is interrupt driven, timing is not an issue. The estimated no of I/Os required is 15. I did search Maxim/Microchip for their port expanders but wasnt able to locate one.

The packaging of the chip is not at all an issue for my design.

Rgds, VSP

Reply to
VSP

Sounds like you have more options, then.

That's surprising. I found them easily, at both sites.

Try google, using...

port expander site:maxim-ic.com port expander site:microchip.com

Okay.

Jon

Reply to
Jonathan Kirwan

I'd use a CPLD. Plenty of them will work at 3.3 V.

Leon

Reply to
Leon

I'd use a CPLD. Plenty of them will work at 3.3 V.

Leon

Reply to
Leon

"Forced"?

The 8255 is a nice chip, but this isn't 1979 anymore. There's lots of choices for GPIO's. Back then there was too :-).

Then (worst case) use a couple of octal latches and a small amount of glue logic. That glue logic would certainly fit inside a GAL/PAL and do address/read/write decoding. You can certainly get octal latches that are 3.3V Vcc and 5V compliant.

If you want power drive outputs then the Sprague/Maxim/TI expander chips are nice. I really like TPIC6C596's for serial in, parallel power sinks out.

Tim.

Reply to
Tim Shoppa

There are many choices, none of them a 8255.

The distributed, low update speed, cascadeable, cpu pin saving solution is a set of 74HC595, serial to parallel shift registers. As many times 8 bits connected to the SPI port.

The flexible compact solution is a CPLD. A MAX3064 with 64 flip flopsin a TQFP44 case gives plenty of flexibility for simple solutions.

The blunt, distributed and fast solution is a set of 74HC574 latches.

Rene

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Ing.Buero R.Tschaggelar - http://www.ibrtses.com
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Reply to
Rene Tschaggelar

Ditto on the CPLD implementation. You might check Opencores to see if anyone did a full implementation of a 8255.

Cheers

of

Reply to
Martin Riddle

On Tue, 18 Apr 2006 01:18:22 +0000, Martin Riddle top-posted:

Are you joking? If I were going to implement 3 ea. bidirectional ports in a CPLD, I sure wouldn't copy the 8255's PITA^H^H^H^Hquirky interface! ;-)

Cheers! Rich

Reply to
Rich Grise

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