Here's another idea for a fast one-shot. This is the just-apply-money version and should get close to 1 ns pulse width and should easily trigger at 150 MHz.
Exposing my contemptworthy ignorance here no doubt, but what exactly is it that is fast about this design, John? And what would its application be?
It would have a leading-edge prop delay of 350 ps, a minimum pulse width just over 1 ns, and would easily trigger at 150 MHz. Integrated one-shots, xxx123 types, are always terrible, even the obsolete ECL ones.
It would be a programmable delay in a number of possible products, including some optical modulators. Just playing right now.
More dollars could certainly do something faster, but as long as customers connect boxes with cables, faster isn't worth a lot. Light just moves too slow.
Any suggestions for a faster one-shot?
What about connecting the + of the RC to Q to speed up the discharge
Pecl only swings about 0.8 volts, up close to Vcc, so it wouldn't help much. That phemt turns on pretty hard, maybe 100 mA with Rds-on a couple of ohms.
Speeding up the discharge would improve rep-rate but wouldn't affect minimum pulse width. I'd need a faster comparator for that, or some different architecture.
The phemt gate driver is a little scary but will work if done carefully.
I could give up a bit of speed and do this in CMOS. There's a 1 ns TinyLogic flop that's 36 cents.
Not from me! I couldn't even design a PID controlled PLL without recourse to the 'net.
On 13/06/2024 4:11 am, john larkin wrote:
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It's just a two transistor emitter-coupled monostable, but with the two transistors as BFR92's run at 10mA, it produces 1nsec pulse without fuss.
Finding the broad-band PNPs to let you translate the output pulse to a useful voltage level is tricky. Phil Hobbs has told us that there is a least one still in production and available.
What a mess. The output pulse width just follows the input pulse width. Unless you change C1, in which case it oscillates.
It's ugly too. Obviously frobbed until it seems to work.
It is a pity it relies on an input pulse shorter than the output - at those speeds it would nicer to have a step input somehow?
piglet
Actually, it doesn't. The input pulse has a full-width at half maximum of 400psec, and the output pulse width is 1nsec, as intended
"Ugly" - in this context - seems to mean "not invented by John Larkin".
It's obviously derived from a simulation I posted earlier, that produced a longer output pulse from the same input. The emitter resistor has been been made smaller to get a 10mA tail current, and the collector resistors scaled down in the same proportion. That narrowed the output pulse,and I tweaked C1 down to 3.3pF to get the 1nsec FWHM output.
There aren't enough components there to represent a mess, if you have any idea what they are doing. If you don't, I supposed that you could get it to oscillate. John hasn't posted his simulation, so we don't know why it oscillated.
If you have a long input pulse you can use a delay line and an AND gate to make a shorter one. That was how I got 0.5nsec +/- 0.05nsec at Cambridge Instruments in their 1985 electron beam tester's beam blanking system.
It's not a one-shot, it's a diffamp. Put in a 50 ns trigger and it will make a 50 ns output.
And it makes the common beginner error of assuming that two transistors are absolutely identical, and at the same temperature, because Spice does that.
The critical 40 mV of diff offeset is derived by the diference between the tweaked power supplies and, I suppose, two 1% resistors. That is really weird. And unsafe.
The dangling wire scraps could roll around and short things.
It's really a slow diffamp, not a one-shot. It will make a nice clean
1 second output, given a 1 second trigger input.
Not that you have posted a sim that illustrates this.
It may not make any sense to you.
R2 and R7 deliver about about 0.8ma of bias current into the divider R13
You don't have to increase the base voltage of Q1 much to bias the pair into an unstable state, in which the emitter current of Q1 rises to 10mA then decays back to 1.5mA.
The excursion into instability is what produces the output pulse.
Not inside a sim. In real life this sort of circuit is always made as a printed circuit board with traces running over ground plane - or at least I've never done it any other way.
It isn't. John could have tried to simulate his "one second trigger input", if he could have worked out what he meant by that.
And it is hard to make a really slow differential amplifier out of a BFR92 long-tailed pair.
He got very excited about the 43mV threshold voltage. Just for fun, I increased R7 in my simulation from 1k2 to 1k5, which doubles the threshold.
The same trigger pulse gave a visually identical output pulse. My guess is that it will be picoseconds later and picoseconds narrower, but I'm not going to make a meal of it by actually measuring the differences.
When I needed a design for a fast pulse generator, Jim Thompson very kindly came up with the goods for me and was happy to do it for free. Jim designed quite a lot of bits and pieces for me over the years. He was a
*genuine* contributor in the true spirit of mutual assistance that the 'net used to be all about. You could learn a thing or two from Jim's exemplary conduct here, Bill. Stop being a condescending wanker and chip- in something useful for a change.
There are some screamong fast CMOS gates and flops around that cost pennies.
Pointed you at the right application note? Most of the work in doing that is finding out what you actually wanted to do.
He was a contract integrated circuit designer, and got paid for anything serious. At one point he claimed that he had denounced me to the FBI for being "dangerously anti-American". That "true spirit of mutual assistance" came with a certain amount of unpleasant baggage.
Just like you do?
And there have been for years. You started this thread with a pencil sketch that included an 10EP51 ($6.53) and an ADCMP562 ($3.15).
Two BFR92 ($0.64 each)and couple of resistors and capacitors can do the same job, if you know what you are doing.
You pencil sketch didn't tell us much about what you were trying to do, or why, and nothing much about the input - "Trig In" as a balanced PECL signal tells us about the signal levels, but nothing else.
As an effort to look like a circuit designer, it wasn't impressive.
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