Another discrete bloodbath

Yeah, fast discretes are going away. I guess all the mass-market stuff is using ICs now.

The c-b junction of the BFT25 was a nice diode, too. I measured 5 fA leakage.

And there seem to be no fast PNPs any more!

I sure hope the SAV parts stay around. I'm planning on using them in a pulse generator. That's a whole nother story.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Yup. I use a lot of CPH3910, BFU520A, BFP640F or H, and a few others, in all sorts of things including TDRs and front ends. Looking to have JLCPCB hold some in stock for us to tide us over.

We've been investigating doing our own array parts, as a first step to doing our own ASICs. TinyTapeout lists a couple of BiCMOS processes with SiGe NPNs **and PNPs** with f_T between 130 and 350 GHz.

That's inconveniently high for what we do--we mostly care about high f_T at low collector current, good beta linearity, and very high Early voltage.

A start would be to make some 130 GHz SiGe NPN/PNP arrays with 0.5 pF or so connected from C to B (on chip) to slow them down a bit so that we can route them without making 30 GHz oscillators.

It'll need more work than just wiring up some BFP640s.

Cheers

Phil Hobbs

I'd really like to do a custom pulse generator output stage IC. A bunch of differential-output laser drivers, like SY88022 and the TI and Maxim equivalents, have all been EOLd at the same time. There must be something going on.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

I wonder how the defense industry can proceed without such gems.

On the plus side, pretty soon we’re liable to be the only ones who can build certain things.

I’d rather be able to buy stuff.

There’s a bit more urgency on pursuing the tinytapeout option now.

Cheers

Phil Hobbs (Budding chip designer)

Which ones? I thought TinyTapeout was just digital CMOS and that you had to use their IO cells (which would ruin the fun).

I'm having a go at doing block for a chip right now:

just CMOS, but we can do custom pads, and someone else is paying for the tapeout so it's good practice, and the IHPSG13CMOS5L is a subset of their BiCMOS process with good NPNs, so hopefully the experience is relevant to the better process for later.

I find that fighting the tools is my main problem.

They've broadened out beyond CMOS and digital. IHP’s SG13G2 process specifically, which has an open-source PDK. I think originally you were right about needing digital I/O, but that improved. I do imagine the I/O drivers may have trouble with 30GHz though.

I am somewhat puzzled about why someone would do a digital design with Tiny Tapeout, other than as a classroom exercise, and the turnaround time is a bit long for that. Maybe to list on your CV?

You presumably aren’t going to be able to run your digital design at

30GHz even if you’re using a 350GHz fT SiGe BiCMOS process (why not?) so it’s just going to be inferior to off-the-shelf parts. But you could easily imagine a custom 130nm analog chip being the best choice for a design.

Relevant bookmarks from 02025-02-23:

130nm BiCMOS Open Source #PDK for analog, mixed-signal and RF design. Work in progress, but they’re doing their first #Tiny-Tapeout already. “SG13G2 is a high performance BiCMOS technology with a 0.13 μm CMOS process. It contains bipolar devices based on SiGe:C npn-HBT’s with up to 350 GHz transition frequency (fT) and 450 GHz oscillation frequency (fmax).” #electronics #hardware

Tiny Tapeout. Mostly just digital #electronics #hardware designs.

for their 130nm and 250nm processes. Their #MPW price for the SG13G2 process for which they offer an open-source #PDK is €7300/mm². “minimum area requirement of only 0.8 mm² for all runs with bold shipment times.” However, no shipment times appear to be in bold, and the normal minimum seems to be 10mm². Looks like the tape-in-to-shipment-time delay for MPWs is about 6 months. You get 40 diced samples. I’m guessing you can do about 2.5 transistors per μm² in the 130nm process, so 0.8mm² is about 2 million transistors.

slides on the first year of the #IHP open-source 130nm SG13G2 #PDK. “a

200mm pilot line for state-of-the-art BiCMOS technologies, operated under industry-like conditions, 24/7, for the provision of prototypes and low-volume production runs.” MIM caps are 1.5fF/μm², or 2.1 for copper.

open-source #IHP #PDK middle of last year: “Designs already submitted for production include a delta-sigma modulator put together as part of Boris Murmann’s electronic engineering course at the University of Hawaiʻi at Mānoa, a 24GHz low-noise amplifier (LNA) from Martin Sander at Ulm University, a different LNA targeting cellular devices from a team at the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), and a simple RISC-V CPU designed by Daniel Schultz and Steffen Reith.” #hardware #electronics

From 02025-02-16:

#toread by Pat Deegan on #electronics #hardware #analog #ASIC design with Tiny Tapeout. Demonstrates how to use xschem.

From 02024-06-02:

40' #video by #Psychogenic-Technologies (Pat Deegan) on designing analog ASIC #electronics #hardware using Tiny Tapeout’s “new analog capabilities”. Basically he’s hacking together a SAR ADC with an 8-stage resistor ladder, although most of that process is omitted; he submitted it to Tiny Tapeout 6 as “WoWA”. I didn’t realize #Tiny-Tapeout had a WebGL GDS viewer. The video has an annoying amount of talking-head filler. He recommends using `tinytapeout_analog_vm` to get started quickly, and Efabless’s video, “Webinar - Analog schematic capture & simulation with Stefan Schippers”, who wrote #Xschem, which he’s using here, with the open SKY130 PDK. He remapped Magic’s and Xschem’s keys to match Kicad. He says both Kicad and Xschem do simulations in Ngspice. Xschem’s UI for exploring simulation results looks pretty interesting, being able to click on a waveform out of many waveforms on a plot to change which waveforms are displayed in other linked plots. He does a little bit of demo of using Magic, which evidently involves typing Tcl commands in a command window as you use the mouse, and he lays out a two-MOSFET mixer circuit in it, with guard rings and everything, after having designed and simulated it first in Xschem. He says Netgen (?) is a good LVS (layout vs. schematic) checker, even though its errors are hard to understand. He recommends simulating your digital blocks with Verilator.

That sounds extremely exciting. I hope to hear more!

Kragen

Haven’t looked into it super deeply yet, but I’d like to start with an NPN/PNP SiGe array, with some sort of arrangement (low current density, caps from base to collector, etc) to keep the speed down.

That might transform the performance of my laser noise cancellers.

Cheers

Phil Hobbs

"The path between the analog pads and your project (the ua pins) is expected to have the following properties:

Resistance: < 500 ohm Capacitance: < 5 pf Max current: 4 mA

You are not allowed to use the metal 5 layer in your design, as it’s used by Tiny Tapeout’s power grid."

So 1/(2*pi*5pF*500Ohm) = 63MHz, that makes it challenging to do anything analog much faster than that until they change those rules.

Learning and practice - if one wants to do something more complicated later, it would be good to at have acquired the knowledge to get the digital part right. Also, having designed chips, it makes it easier to guess what is inside commercial chips, which can help when the datasheets are vague.

You probably could, if you make it as something like ECL. It will use a lot of power though, and you'd presumably need a clock.

So far, I don't think actually using the chips in a product is the point of the exercise, it is more about developing skills and finding and fixing problems with the open source toolchain.

For analogue, especially in CMOS, I think I prefer 0.25um or 0.18um rather than anything much smaller. Once the supply voltage is so low that it is only about twice the threshold voltage, you can't fit much signal in. Also the gate oxide starts to be leaky. Inductors, resistors and capacitors just get more and more expensive but not any better as the process gets smaller.

This is something I don't understand - why only 40 samples? If they process only one 8 inch wafer, I would expect several thousand chips to result, though if you have only one copy of your design on each reticle then I suppose maybe there would only be about 40 copies - but why not process more than one wafer - a normal batch would be like 25 wafers I would think, and even for prototypes I would expect them to process say

5 wafers. The 40 samples is annoying for chipalooza, as it means each designer probably only gets 2 parts, so one would constantly be in fear of damaging them.

The nice thing about chipalooza compared to TT etc. is that you can directly access some bondpads, use thick metal etc.

Which (open pdk) process are you looking at that has good PNPs? IHPSG13G2 only has good NPNs I think:

You can probably mostly avoid needing to slow it down if you can keep the feedback loops on-chip.

If you can't get access to the BiCMOS process cheaply, or if just NPNs aren't enough, then maybe 0.13 CMOS would be good (fast) enough to implement a current mirror with programmable ratio (a multiplying current DAC) and you could use that to mirror one photodiode current to cancel another photodiode current, by adjusting the mirror ratio until it matches.

If you want to try it, there is a docker image with xschem, klayout, ngspice and a very slightly out of date version of several PDKs here:

I don't understand or trust docker so I installed it inside a separate debian VM using the version of docker packaged by debian, and that worked.

In your directory where you put xschem schematics, make a xschemrc file comtaining:

source $env(PDK_ROOT)/ihp-sg13cmos5l/libs.tech/xschem/xschemrc # Add current directory to xschem library path append XSCHEM_LIBRARY_PATH :[file dirname [info script]]

there is a script sak-pdk that lets you change process (by setting some environment variables), but you can then make a file called .designinit in the designs directory, which you can use to set those environment variables so you don't have to use sak-pdk each time you start work.

There is a forum where you can ask for help, here:

One thing that I think would be fun, and useful to other people, (and that you would be good at) is an integrated fibre-optic front-end - I have found a few papers where people have made a photodiode in a CMOS process, and its associated electronics, and have managed to receive several GB/s over a short fibre from a SFP transceiver at 850nm, in spite of the CMOS process being not really ideal for making photodiodes. This might be useful to other people for testing fast digital blocks, since the IO cells (that people are allowed so far, on e.g. TT) are often pretty slow, but if one can get at the die, and point a fibre at it, then one could bypass the slow IO cells, for input at least.

You might find this podcase episode interesting:

Oof. Your post was extremely valuable overall, but this was one of the most valuable things about it. Thank you.

That’s a really good question. It would be surprising if IHP’s MPW business had a high enough volume of *different* designs that they could do *one* copy of each per wafer, wouldn’t it? And, even then, the stepper that’s exposing the wafer would have to change masks every exposure, right? You can’t just expose the photoresist over the whole wafer at once, can you?

Yeah, it sounds amazing.

Kragen

I don't know the details for their process, but I think that on some processes, the wafer is exposed with multiple copies of a ~25mm x 25mm "reticle" (that is made by 5:1 optical reduction from a 125mm x 125mm mask), so the minimum number of one design would result from having one copy on the reticle, resulting in maybe 40 copies.

The major cost for prototypes is the masks (several hundred thousand dollars) rather than the wafers (often less that $1000 each including processing), so I don't think more than one mask would be used on one photoresist layer of a wafer. More likely the reverse: For prototypes, I think there are some tricky techniques that use one mask several times, for multiple layers, and just cover up the part of the mask that is for the wrong layer and expose a smaller reticle each time.

I guess perhaps for prototyping, there could be chips with different die sizes on the same reticle, and so, some parts from each wafer might get a saw cut through them.