analog failures

Den tirsdag den 14. februar 2017 kl. 23.47.11 UTC+1 skrev John Larkin:

It does seem like when analog designers get to design the digital parts of a chip it often ends up with a hairball of hazards and weird quirks

Yup. It's all Jim's fault.

I wondered who would be the "snarker".

Actually, when I have anything exceeding combinational, I have a buddy who cranks out an SPI bus for me.

As for _device-level_ logic design, I am quite good at that... after all _device-level_ IS analog... ask Motorola/ON-Semi about my 74HC designs. ...Jim Thompson

That was always my experience with part from NatSemi. Pure analog was good, pure digital was good, mixed mostly was a mess.

Mixed signal design is difficult, and doing it on a chip, where it is harder to keep the noisy digital bits away from the sensitive analog bits, wouldn't have made it any easier.

Sadly, mixed signal design can do a lot more than pure analog or pure digital, so if you have got something complicated to do, that tends to be what you end up doing.

We recently designed-out the AD7793; the SPI interface is hopelessly botched.

There was some other ADI chip, a DAC I recall, that has a bit in one register that changes which edge of the SPI clock is active! It's not clear what the powerup state of that bit is.

I had to do this:

---------------------- | | data----------------- --------------------

--- | | clock----------------------- ------------------------------

to make sure it would work.

The weird stuff always happens at the interface between designers that each know their stuff, but don't know the other's stuff.

It was never the problem of digital noise coupling into the analog portions but the digital totally mixed up, like the LM75 going into a state where only a power cycle helps to get it working again. This can be caused by noise on the I2C signals. I had the same with a part from Microchip. It has a config bit to automatically reset its I2C interface after a timeout period without any activity on the bus. This bit is reset after power on. So if the interface goes gaga because of a poor POR you never get it working.

No, no. I was blaming you for the _analog_ problems. You sly devil.

Sno-o-o-ort >:-} ...Jim Thompson

IME most analog failures are caused by ESD and that is often squarely in the court of the board level designer.

Upsets without subsequent chip damage are also considered a fault where the function is mission-critical. That is very often due to EMI.

I2C is a bus I try not to use if it can be avoided because of various hang-ups. SPI is much more robust IME and, therefore, that is what I prefer.

Oh-oh. Sounds like they built in a loose cannon for a sledgehammer. However, a poor POR is something the circuit designer should take care of. Never trust any on-chip POR/BOR. Ever.

I prefer SPI too, and it's faster, but lots of people design terrible SPI interfaces, bad logic design and bad clock/data circuits. Every SPI should have schmitt inputs and safe timing margins. Maybe cooking a digital design into an analog process causes compromises, but I suspect it's just sloppy engineering.

The little NXP ARM chips, LPC1768 and such, seem to do POR right.

All the FPGAs that we have used lately, ditto.

You can connect one of those ARMs, or an FPGA, to a serial flash chip and have the whole thing boot up reliably.

I think that a lot of analog chip designers outsource digital IP modules, things like Ethernet, PCIe, SPI, PLLs, like that. Similarly, a uP or FPGA designer may outsource an ADC to tuck into one corner of the chip. The result is bad documentation, no support, and bugs.

We use some ARM chips that have onboard ADCs, and NXP seems to know almost nothing about them.

Hardware is quickly catching up with software!

Even they seem to have their oops moments.

Quote page 9: "POR reset value of the event router STATUS register corrected"

Quote page 18:

"Problem:

The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller.

Work-around:

None."

End quote

If you use certain FPGA you'd first have to call the people at your energy provider that you are about to turn it on :-)

Nah, 0.9 volts at 15 amps isn't a lot of power.

It's your bank that you have to call before you design in a big FPGA. Some of the chips cost over $10K.

Digikey offers one Virtex for $54,976.08000. Why steal diamonds when a reel of FPGAs is worth millions?

Den onsdag den 15. februar 2017 kl. 19.53.11 UTC+1 skrev John Larkin:

a couple of zeros was added to make up the numbers for a military contract ;)

That's unfortunate, particularly because if you just take a lickum-stickum approach to the design process the analog bits won't work nearly as well as you'd like.

Good advice if the chip has no reset pin. :-(

What, you think anyone would actually pay for illegitimate ones?

They depreciate faster than cars!

Tim