analog failures

The problem is that the issue is often not controlled by the quality of the design but by that of the circuitry inside an IC, so out of the hands of the board level designer.

I2C is a great idea. It's just the implementation that often isn't sufficiently rugged.

SPI parts have a chip select pin, so there should be no doubt about a part being selected.

Deselecting a part returns it to a defined state (unless it's made by Analog Devices.)

Device selecting 21 devices is a RPTIA. Many MCUs, incuding ARMs, only have one true SSN pin.

Returns the I/O interface to a defined state, anyway. The nine clock and a STOP thing usually works on I2C, unless more than the I2C interface is screwed up. All bets are off on either bus if multiple masters are used, though sometimes it's unavoidable.

We often bit-bang the SPI chip selects from regular port pins. Or even use a decoder.

Not in the AD7793!

That works for really trivial systems. It's kinda tough booting systems over bit-banged SPI, though. I often have a situation where the DSP is booted from flash but the DSP is also a slave to a uC (and the uC has to be able to update the flash). Bit banging isn't a great solution.

Are you positive there isn't something else screwed up in the interface. I've never used a 7793 but your description does sound bad.

We use press fit in running production. I have never heard about failures, once the process is running correctly

Cheers

Klaus

They usually happened on units where boards were pulled and plugged often. Also on systems that were exposed to very rough transport like hundreds of miles on washboard roads in a raggedy old truck. Soldering those motherboards fixed that problem. The press-fit had been performed professionally at a company that specialized in this technology but it still failed at times.

Well, obviously we need to do what it takes to boot a system. But port-banging chip selects later works fine. Once a target is chip selected, then we sometimes fire off an SPI engine (uP resident or built in an FPGA) or just bang the entire SPI transaction. On a 600 MHz ARM, we can software bang SPI as fast as most chips will accept it.

I often have a situation where

We typically let an ARM boot its code off a serial flash. Once that's up, it usually reads more of the flash to program FPGAs, which is essentially SPI.

It has a bit counter that frames SPI packets. The counter is cleared at powerup but is not reset by deselect. So if it gets out of sync, the interface is hosed. It tends to slip counts when it gets cold, and it really doesn't like sharing the SPI interface with other chips.

The fix is to use a TI chip.