An other Microchip screwup on teh 18F14K22

The whole idea behind Verilog and in particular, VHDL, is design correctness and verification. It's *not* software, though I've seen enough managers who believe it is (and assign C programmers to logic design ). The issue is not one of "mindset" that all designs have bugs, rather that all designs are so complicated that it becomes impossible to test every combination of features.

All of our designs were in VHDL and the simulation environment (architecture models, simulator, and "test benches") was C++. Much of the verification started out with random settings of registers and random sequences of instructions. This works well for CPU sorts of things, where pretty much any sequence of instructions and data will produce "interesting" results. It tends to get messy when working with I/O, where many settings and data combinations will cause failures (It hurts when I do that => don't do that). Verification is not a simple problem. It's also often seen as a necessary evil and swept under the carpet.

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The underlying idea of using some programmable logic rather than Special =46unction registers to select or even perform the various pin functions. It could even be in a separate program space. This could really help with all of the various serial busses that are popular now. It may even allow better allocation of ADC/DAC I/O.

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I don't see how Muxes are all that big of a deal, particularly after you have FPGA fabric connected to the I/O.

Some have routable analogs, most restrict the pins these functions are on very tightly.

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To maintain any analog capability it would have to be at least one transmission gate (analog switch) remove.

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The CPLD layer could allow lesser restrictions, which may then allow more convenient routing of the board.

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So what? Pass gate logic is quite normal. In fact, FPGAs would be impossible without them (that's how routing is done).

Nonsense. The limitations on analog routing is a matter of noise, cost, and utility.