ADC layout screwup

Sounds like VREF noise. What happens near full scale?

Something else saturates at the moment--I need to change a couple of resistor values. But it gets suddenly worse near 1/4 scale, rather than gently increasing. So it might be SDO crap getting into Vref, good point.

Cheers

Phil Hobbs

Some of those TI parts, and others, do the successive-approximation logic as the data is being clocked. So even if the analog input is sampled before the data is clocked, noise could affect the conversion, even though it theoretically can't affect the sampled value. But VREF is (probably) used all through the conversion.

Offset binary versus signed output?

What does it sound like if you load the data into an audio editor as a .raw file and hit 'Play'?

-- john, KE5FX

It's twos-complement. Potentially a nice part, if you don't screw up the layout. :(

Dunno. Based on the scope trace, it wouldn't be a pure tone, for sure.

Cheers

Phil Hobbs

It could be a digital problem. SPI can be tricky.

What's fun is to use the wrong clock edge and have things usually work.

The first thing I check for is Errata, but there is none. It's a National part if that matters. But It does sound like it might be a diff vs single ended mode selection problem, or your inputs are crossed some how. I doubt a noisy vref would cause that much of a problem.

The second to last page of the data sheet has layout guidelines, and looking at the pin out it's hard to imagine a layout problem with the clock. Have you tried terminating the clock into some resistance?

Cheers

At liberty to share the layout? (Via email if not NG)

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

Unfortunately not. (It would be good for my humility if I could--this isn't the only problem I didn't catch.)

Cheers

Phil Hobbs

Maybe. I didn't write the code, so I'll try switching SPI modes and see if it gets better. (So scientific.)

Cheers

Phil Hobbs

We used one ADI part that had a bit in a control register that selected which clock edge the SPI interface uses. Think about that for a few seconds. Another ADI part did *not* clear anything in the SPI interface (not even the bit counters or shift registers) when CS went false.

We've also had clock edge problems on some SPI parts for no observable reason. Analog Devices seems to do the digital parts of mixed-signal stuff badly. TI is much better. Makes sense.

The problem with TI lately is that when you need help, they'll say "Oh, that's a National (or B-B) part, nobody knows anything about that."

Are your clock and CS lines short or terminated?

Am 16.06.2017 um 22:57 schrieb Phil Hobbs:

Any chance that it might be a signal voltage level mismatch of some kind? We've had similar problems...

cheers Gunther

To me this sounds like poor grounding and/or bypassing. Assuming the IC designers didn't mess up.

If you really suspect SPI pollution try AC termination at the far end of the SDO line and AC termination at the ADC for SCLK. If you have only a few inches of trace each then 33pF or 47pf in series with whatever the microstrip calculator shows as line impedance should work.

Bypass VREF really well, shortest path to GND plane. 0.1uF right at pin,

You need a low-Z reference source. If the analog inputs are driven hi-Z (not a good thing at all) there should be some sort of filter cap right at the input pins. Such converters can spew impressive re-charge spikes on their inputs.

I know you wrote you can't share the layout but maybe just the immediate ADC area?

AC termination can have strange effects for a burst clock like SPI. Series termination at the source is probably better.

Good SPI chips have schmitts on all their inputs, but many don't. We have fixed flakey SPI interfaces by adding a 47 pF cap from SCLK to ground at the end, without ever understanding why. Scope probes sometimes fix (or break) SPI interfaces.

We did one parallel ADC to FPGA interface at 250 MHz and the FPGA guy got the clock edge wrong. It usually worked!

It shouldn't, as long as you do not make the capacitor unnecessarily large.

Source can work as well but that requires cuts. It also requires that the line impedance does not change much along the way.

Or a finger, after drinking 2-3 bottles of Belgian Tripel. It worked. Now I brew my own Belgian Tripel.

I had a converter chip from a top notch manufacturer which only worked with SCLK reversed. The app engineer was puzzled and suggested to leave it that way. Luckily this was only a prototype system.

SPI = Seriously Problematic Interface.

Sometimes Proper Input

Phil,

Some ADCs can have very odd inputs whose loading changes in odd ways and over time as the conversion takes place.

Are you driving the ADCs with the correct Z. Sometimes a cap across the differential input can help hold the signal steady during the conversion.

But you prob know this already. m

Den mandag den 19. juni 2017 kl. 02.30.12 UTC+2 skrev John Larkin:

the problem start with the expectation that SPI is a standard, it is really just short hand for a couple of wires one of them probably a clock

ry

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ng

the "wrong" clock edge depends on whether you need setup or hold