adding FPGA grounds

ensen

e:

snipped-for-privacy@highlandsniptechnology.com:

alls on an FPGA

o reduce ground

states of all such

turn the grounds

ld add at least

hink the general

odern BGA FPGAs

r unused pins.

onnected to,

cb

lp with cooling

fabric; so, probably not much difference.

ductive.

off??

uld

itly stated otherwise in the spec.

as to pick something safe

here it's connected to.

s have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advanta ge

that

ogic. I

w that

rd "1"

mpiler

s for cooling. Especially with output buffer cells, heat transfer to pin/pa d is much higher than to any other cells. With smaller geometry, interconne ctions are getting smaller, but the buffer cells need to be relatively bigg er to maintain the current capacity. If anything, you can try to space out cells as much as possible, but i doubt you can do any better than the compi ler.

ng, perhaps.

ns are connected to a plane it might help with cooling"

robably not much difference.

han just the physical pads.

That was YOUR uninformed post spouting nonsense. The electrical connection s are made by MOSFETS when turned on and have nothing to do with thermal co nductivity.

and so not about "cells" on the chip. The issue is the thermal connection between the board and the chip through the balls.

e the same solder balls. The pads on the PCB can be thermally connected to power planes that spread the heat across the board helping to lower the the taJA. It is hard to make pads any bigger. The issue is providing either a v ia in pad or a via with a WIDE dog bone (more of a football) to the adjacen t via or vias. In fact, if adjacent pins are picked, they can be "pooled" a nd connected to one another (as well as any pins on the same power rail) wi th all vias in the area connecting the common copper to the same power plan e. This would provide the best cooling in aggregate. I guess you could call this a "wide" pad.

d you will get some additional cooling.

her cells.

ed. NOTHING The balls are just connections between two PCBs. The chip is co nnected to one PCB and traces and vias in that PCB connect the chip I/Os to the balls on the other side of that PCB which are then soldered to the PCB you design. No good thermal connection is made over the rather thin traces inside the BGA package. The heat is conducted through the substrate to the balls.

s directly to the internal PCB. Take a look at this page with good illustra tions.

fabric.

Which means nothing.

I'm giving up on you. You literally seem to have no understanding of what is going on inside an IC.

stensen

Lee:

snipped-for-privacy@highlandsniptechnology.com:

balls on an FPGA

to reduce ground

i-states of all such

nd turn the grounds

ould add at least

think the general

modern BGA FPGAs

for unused pins.

connected to,

pcb

help with cooling

he fabric; so, probably not much difference.

onductive.

or off??

would

icitly stated otherwise in the spec.

has to pick something safe

where it's connected to.

ols have to keep them deactivated, it cannot assume unused pins are connect ed to ground and turn them on as extra grounds even if it would be an advan tage

ff that

logic. I

now that

hard "1"

compiler

lls for cooling. Especially with output buffer cells, heat transfer to pin/ pad is much higher than to any other cells. With smaller geometry, intercon nections are getting smaller, but the buffer cells need to be relatively bi gger to maintain the current capacity. If anything, you can try to space ou t cells as much as possible, but i doubt you can do any better than the com piler.

ling, perhaps.

pins are connected to a plane it might help with cooling"

probably not much difference.

than just the physical pads.

ns are made by MOSFETS when turned on and have nothing to do with thermal c onductivity.

on and so not about "cells" on the chip. The issue is the thermal connectio n between the board and the chip through the balls.

s.

ave the same solder balls. The pads on the PCB can be thermally connected t o power planes that spread the heat across the board helping to lower the t hetaJA. It is hard to make pads any bigger. The issue is providing either a via in pad or a via with a WIDE dog bone (more of a football) to the adjac ent via or vias. In fact, if adjacent pins are picked, they can be "pooled" and connected to one another (as well as any pins on the same power rail) with all vias in the area connecting the common copper to the same power pl ane. This would provide the best cooling in aggregate. I guess you could ca ll this a "wide" pad.

and you will get some additional cooling.

other cells.

ured. NOTHING The balls are just connections between two PCBs. The chip is connected to one PCB and traces and vias in that PCB connect the chip I/Os to the balls on the other side of that PCB which are then soldered to the P CB you design. No good thermal connection is made over the rather thin trac es inside the BGA package. The heat is conducted through the substrate to t he balls.

ers directly to the internal PCB. Take a look at this page with good illust rations.

g fabric.

What means the gold wires or copper traces of internal PCB conduct heat bet ter than the interconnecting fabric.

is going on inside an IC.

Then inform us what's going on inside.

e:

ristensen

e:

d Lee:

ev snipped-for-privacy@highlandsniptechnology.com:

ed balls on an FPGA

ng to reduce ground

tri-states of all such

and turn the grounds

could add at least

I think the general

on modern BGA FPGAs

t for unused pins.

is connected to,

he pcb

t help with cooling

the fabric; so, probably not much difference.

conductive.

n or off??

t would

plicitly stated otherwise in the spec.

it has to pick something safe

er where it's connected to.

tools have to keep them deactivated, it cannot assume unused pins are conne cted to ground and turn them on as extra grounds even if it would be an adv antage

tuff that

of logic. I

know that

a hard "1"

e compiler

cells for cooling. Especially with output buffer cells, heat transfer to pi n/pad is much higher than to any other cells. With smaller geometry, interc onnections are getting smaller, but the buffer cells need to be relatively bigger to maintain the current capacity. If anything, you can try to space out cells as much as possible, but i doubt you can do any better than the c ompiler.

ooling, perhaps.

d pins are connected to a plane it might help with cooling"

o, probably not much difference.

e than just the physical pads.

ions are made by MOSFETS when turned on and have nothing to do with thermal conductivity.

tion and so not about "cells" on the chip. The issue is the thermal connect ion between the board and the chip through the balls.

ads.

have the same solder balls. The pads on the PCB can be thermally connected to power planes that spread the heat across the board helping to lower the thetaJA. It is hard to make pads any bigger. The issue is providing either a via in pad or a via with a WIDE dog bone (more of a football) to the adj acent via or vias. In fact, if adjacent pins are picked, they can be "poole d" and connected to one another (as well as any pins on the same power rail ) with all vias in the area connecting the common copper to the same power plane. This would provide the best cooling in aggregate. I guess you could call this a "wide" pad.

l and you will get some additional cooling.

r other cells.

igured. NOTHING The balls are just connections between two PCBs. The chip i s connected to one PCB and traces and vias in that PCB connect the chip I/O s to the balls on the other side of that PCB which are then soldered to the PCB you design. No good thermal connection is made over the rather thin tr aces inside the BGA package. The heat is conducted through the substrate to the balls.

lders directly to the internal PCB. Take a look at this page with good illu strations.

ing fabric.

etter than the interconnecting fabric.

at is going on inside an IC.

I did and you make irrelevant comments. That is why I said you have no ide a how a chip package conducts heat to the outside. It's not through the bo nd wires just as it is not through the copper traces. Do you understand wh at I said about the "squares"?

Instead of thinking of a wire as "conducting" think of it as a resistance. After all, everything is a resistance, it's just a question of how much. A wire with a lot of length relative to it's width will not conduct heat we ll from one end to another.

If some Nvidia ^H^H^H^H^H Xilinx documents proposes, consider it. Otherwise not!

ote:

e:

Christensen

Lee:

Ed Lee:

krev snipped-for-privacy@highlandsniptechnology.com:

used balls on an FPGA

eing to reduce ground

e tri-states of all such

e, and turn the grounds

We could add at least

ut I think the general

e on modern BGA FPGAs

est for unused pins.

t is connected to,

the pcb

ght help with cooling

of the fabric; so, probably not much difference.

ly conductive.

on or off??

hat would

explicitly stated otherwise in the spec.

o it has to pick something safe

tter where it's connected to.

e tools have to keep them deactivated, it cannot assume unused pins are con nected to ground and turn them on as extra grounds even if it would be an a dvantage

stuff that

t of logic. I

't know that

g a hard "1"

the compiler

l cells for cooling. Especially with output buffer cells, heat transfer to pin/pad is much higher than to any other cells. With smaller geometry, inte rconnections are getting smaller, but the buffer cells need to be relativel y bigger to maintain the current capacity. If anything, you can try to spac e out cells as much as possible, but i doubt you can do any better than the compiler.

cooling, perhaps.

sed pins are connected to a plane it might help with cooling"

so, probably not much difference.

ve.

?"

ore than just the physical pads.

ctions are made by MOSFETS when turned on and have nothing to do with therm al conductivity.

ection and so not about "cells" on the chip. The issue is the thermal conne ction between the board and the chip through the balls.

pads.

ds have the same solder balls. The pads on the PCB can be thermally connect ed to power planes that spread the heat across the board helping to lower t he thetaJA. It is hard to make pads any bigger. The issue is providing eith er a via in pad or a via with a WIDE dog bone (more of a football) to the a djacent via or vias. In fact, if adjacent pins are picked, they can be "poo led" and connected to one another (as well as any pins on the same power ra il) with all vias in the area connecting the common copper to the same powe r plane. This would provide the best cooling in aggregate. I guess you coul d call this a "wide" pad.

all and you will get some additional cooling.

for other cells.

nfigured. NOTHING The balls are just connections between two PCBs. The chip is connected to one PCB and traces and vias in that PCB connect the chip I /Os to the balls on the other side of that PCB which are then soldered to t he PCB you design. No good thermal connection is made over the rather thin traces inside the BGA package. The heat is conducted through the substrate to the balls.

solders directly to the internal PCB. Take a look at this page with good il lustrations.

cting fabric.

better than the interconnecting fabric.

what is going on inside an IC.

ea how a chip package conducts heat to the outside. It's not through the bo nd wires just as it is not through the copper traces. Do you understand wha t I said about the "squares"?

Yes, copper pads, or big and width traces. Nothing through cell to cell in terconnecting fabric.

Won't there be a problem at startup, when the IOs are undefined? Then you may short an output to GND destroying the port.

We once did a thorough investigation into a microcontroller startup to clarify how the outputs would behave during ramp up of VDD. Below about 2V it was undefined, so needed to add resistors to pins connected to GND

My guess is that a FPGA has the same kind of ports and reset circuitry, so it will have the same issue

Cheers

Klaus

may short an output to GND destroying the port.

Unconfigured outputs are typically inputs with a light pullup resistor (oth er than the Spartan 3 devices which had a flaw that resulted in a rather st iff pullup resistor). How would that present a short? Grounding a pullup is a short?

arify how the outputs would behave during ramp up of VDD. Below about 2V it was undefined, so needed to add resistors to pins connected to GND

So all inputs need a series resistor on FPGAs because you never know the st rength of the driver? Our design has switch inputs. If a switch is connec ting to ground on power up this will cause a problem? I've never heard any one make that claim.

o it will have the same issue

But that would be a guess. FPGAs are designed with configuration in mind, in particular the fact that not only do they need to deal with the power up sequence but the whole time a device might be unconfigured. I don't think assumptions are valid in this case.

There is

Nice links, thanks.

I have a time-critical async signal ripping through this FPGA, and there is also a 40 MHz clock and some SPI activity. Ground bounce will add jitter to the critical signal. The ground pins are clustered towards the center balls, so maybe we can create a bunch of fake, low-Q grounds around the edges of the chip, with better connections to the ground plane. We could even play with drive strength.

We'll try it and see what happens.

I do not see the mention of the ramp up and how the pins are controlled. In any case, since the voltage is low, and the IO FETs are limited size, one can calculate the max current running during the small duration of time whe n there might be a short and that current might be small and thus irrelevan t. Again, "might"...

Cheers

Klaus

ou may short an output to GND destroying the port.

ther than the Spartan 3 devices which had a flaw that resulted in a rather stiff pullup resistor). How would that present a short? Grounding a pullup is a short?

During ramping of the VDD/supply rail, the reset circuit has not kicked in yet, and the voltage is so low that the CMOS states is not known

clarify how the outputs would behave during ramp up of VDD. Below about 2V it was undefined, so needed to add resistors to pins connected to GND

strength of the driver? Our design has switch inputs. If a switch is connec ting to ground on power up this will cause a problem? I've never heard anyo ne make that claim.

so it will have the same issue

in particular the fact that not only do they need to deal with the power u p sequence but the whole time a device might be unconfigured. I don't think assumptions are valid in this case.

Configuration, yes. But that is a SW configuration, not HW. States are load ed during boot, right?

Cheers

Klaus

uch

ds

you may short an output to GND destroying the port.

(other than the Spartan 3 devices which had a flaw that resulted in a rathe r stiff pullup resistor). How would that present a short? Grounding a pullu p is a short?

n yet, and the voltage is so low that the CMOS states is not known

During ramp up FPGAs are very current sucking. I'm not sure a handfull of I/Os shorting would produce much more draw than the chips do anyway. Consi der the effective capacitance of all the transistors on the chip having to be charged up.

o clarify how the outputs would behave during ramp up of VDD. Below about 2 V it was undefined, so needed to add resistors to pins connected to GND

e strength of the driver? Our design has switch inputs. If a switch is conn ecting to ground on power up this will cause a problem? I've never heard an yone make that claim.

y, so it will have the same issue

d, in particular the fact that not only do they need to deal with the power up sequence but the whole time a device might be unconfigured. I don't thi nk assumptions are valid in this case.

aded during boot, right?

The configuration (not sure what "states" are or what "boot" is) is loaded during configuration. However, there are circuits to assure the I/O pins a re held in a defined state. I can't say what they do during the power up p eriod. My concern with that phase has always been the power consumption wh ich can be very spiky and quite high.