Mike Noone: You would be well advised to make at least a four layer board for this part. It is generally not possible to properly bypass the supply leads to a device of the package type shown in the referenced data sheet if you try to use a 2 layer board. Trust that myself and others that have also suggested this to you really do know what we are talking about. By the time you end up futzing through your third spin of a two layer board trying to make it work you will have already spent the money it would have taken to get the first pass on a four layer board.
Er, I think the above paragraph needs further elaboration. ;-) I have seen some sorry LDOs have problems with too low ESR, but geez, bypass of a digital circuit having a problem with too low ESR?
Mike, if you want random data, then you can indeed save a lot on the caps, just use 100nF. And also a 2layer board is sufficient. Don't call it precision measurement.
You might consider a less speed-intensive way to get your random numbers. For instance you could measure two time intervals in a row and concatenate the results. For example if you want a 16-bit result, make two 8-bit measurements. That way your clock only needs to be 1/256'th the resolution, so you can use some cheap and common counters to do the job.
This is usually done by modulating the laser and extracting the beat frequency-- not by direct timing. It's a few bazillion times easier.
I know this isnt the answer you asked for, but you might want to consider starting over with the design and use a bit more cleverness and a bit less brute force. Do a little research and see how others have handled similar measurement problems. Those kinds of things have been done as far back as 1970, with 200MHz transistors, so we know it's doable with relatively sedate parts.
Handling picosecond signals requires extreme care-- not something you can do first-off with a 2-layer board. Look at PC motherboards-- they have been having to use four or more layers since they went to 100MHz bus speeds-- you're trying to handle signals 10 to 50 times as fast with two layers. Just isnt going to happen.
If you remember your basic AC circuits the paragraph should be self explanatory. The problem is the parallel resonance which creates an impedance peak. This can destroy the low impedance of a power distribution system near the resonance frequency. If you remember that the shape of a resonance is determined by the resistance in the circuit which acts to damp resonance, you will realize that you need some minimum level of ESR in the cap to lower the resonance peak. I have not found any resources on the web to point you to which demonstrate this, but the course I took with Lee Ritchey showed this in theory, simulation and in real measurements.
It is important to remember that the ESR of a capacitor has little to do with its decoupling ability. It sets the floor at self resonance, but the remainder of the impedance-frequency plot is determined by the capacitance and parasitic inductance.
Parallel resonance in power distribution systems is very real.
You can get free tools that support many layers. FreePCB seems to work ok.
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As to the cost, I think if you look around rather than assuming, you will find any number of vendors who will provide low cost multilayer PCBs.
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$50 for qty 1, 4 layers
Like others have said, in general 2 layer boards are not a good idea for sensitive circuits. It is possible to flood fill the signal layers with power and ground to provide high frequency capacitance, but this will not be as good as multilayer boards because the layers will be spaced so far apart.
You need to think about what is the goal of decoupling. A chip has a power surge. You want the local capacitance to provide the current for this surge, rather than yank on a supply line that is really an inductor in series with an ideal power source. The ability to prevent a voltage drop at the IC is directly related to the ESR, and less is more. ESR has everything to do with decoupling.
Granted it is not your theory that you are trying to defend, but it lacks sound science.
Indeed. Somewhere recently I read a nice explanation of that, but it's easy enough to simulate in Spice or RFSim99 or ... If you use two widely-spaced capacitance values for bypassing, the impedance peak at a frequency between their series resonances can be rather high. By using values that are close enough together (such as your suggested 0.1, 0.01 and 0.001uF, or even more different values covering a similarly wide range), you can control the maximum impedance over a fairly wide range of frequencies. The close-spaced power-ground planes are great for the really high frequencies, as you say. It's also helpful to put those power and ground planes close to the surface where the parts to be bypassed are. A via introduces 1/16 inch (1.6mm) of spacing between a part on one side of the board and a plane on the opposite side. That can be (almost certainly WILL be) a significant fraction of a nanohenry, an impedance likely higher than the ESR at even 100MHz.
Note that for a given capacitance, you can lower the Q by either LOWERING the inductance or RAISING the resistance. Lowering the inductance has the added benefit of raising the resonant frequency, allowing better bypassing at higher frequencies. Use parts with lowest possible inductance; lay out the board with the lowest possible additional inductance.
Back to the OP's question: I'd say a chip designed to require such high bypass capacitance is a very poorly designed chip. In addition, there is practically NO reason you should have to put that much capacitance really close to the chip; power fed through an effectively very low impedance transmission line from a low impedance power supply at a distance will still look like a low impedance at the chip, even at low frequencies.
The TDC is to measure with sub-nanosecond resolution, not to handle sun-nanosecond signals. For sure, jitter of additional logic is a problem, but the TDC is normally in the front of the signal chain.
What you are doing here makes sense. The smaller caps have less ESR and ESL, so you are providing some bypass in frequency range where the large caps have lost their edge due to ESR/ESL. Now granted it is not much bypass since the cap is small, but it is better than nothing.
None of which are 0.01uF, so I don't understand what you're trying to tell us.
A quick check of digikey shows that the lowest voltage rating of
0.01uF caps in 1206 or larger cases is 25 V. If you look at 01005 through 0805, the lowest voltage rating is 6.3 V (for 0201 and 01005 sizes). Although I'm not sure what that tells us, either.
High Q circuits make the troughs deeper and peaks higher. To achieve a moderate Q circuit, one must minimize ESL rather than increasing the ESR, since it was already demonstrated that ESR always creates a ripple voltage as shown in Equation (12). Furthermore, reducing the ESL will help avoid any unwanted resonances between the board power plane capacitance and the decoupling capacitor inductance.
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