47uf decoupling caps?!

Okay, here's one last comment:

The precision might be written down in the design specs, and may indeed SEEM necessary, but:

(1) Random numbers and laser rangefinders have been done with hardware that's 1000 times slower than this. Measuring distance with direct time-of-flight techniques can be done, but it's really a very hard way. This stuff was being done in 1955 with vacuum-tubes for sakes! All you do is FM your oscillator at a high rate. The echoed signal comes back a bit delayed in time, and therefore in frequency. The frequency difference is easily measured as it's in the low kilohertz range and gives a direct, exact distance readout. No picosecond-capable and expensive components. Stuffable into a radar-gun. Runs off milliwatts.

(2) There's NO WAY you're going to get that kind of precision with a dual-layer board. At the 20 picosecond level you're talking about frequencies in the FIFTY GIGAHERTZ region, which requires very carefully crafted striplines and waveguides, usually on a microscopic hybrid IC substrate. I'd be very surprised if with your circuit board you can get 1/1000 th the bandwidth you need to utilize this chip.

(3) How are you feeding in the signals? At 20 picoseconds youre talking about many gigahertz of bandwidth. You can't run those kind of signals thru coax.

(4) Any talk of 47uF capacitors around a 20 picosecond circuit is INSANE! To form a usable bypass at 50GHz you're talking maybe about a

I know you don't want to hear this, but you and whover wrote the spec need to sit down and face the facts.

You're not going to get there from here, not by a factor of at least

Both your applications can and have been done for many decades with

The goal of electrical engineering is to do as much as possible, reliably, with the simplest and cheapest design.

Your plan seems to be doomed to fail, by a factor of 100 to 1000, with complex, shaky, hot, and very expensive design.

Not to put too fine a point on it, but youre following a path to absolute failure-- a complete rethink and redesign is the only way out.

I realize you may have been given this chip as a fixed target, but sometimes you have to go back to whoever chose this chip and these designs, and say, hey, people that know better say we're not going to get there from here by this path.

I do ps-resolution delay generators and time-digital converters on 6 or 8-layer pc boards, with delay jitters in the single digits of ps and TDC jitters in the 25 ps RMS range, so it can be done. I agree that double-layer boards would result in a huge performance hit. The chip he proposes to use seems to be very Vcc sensitive, and it likely draws big current spikes and probably has steps of Vcc current, so it may need a lot of energy storage in its bypassing.

The first TDC I did was done in CMOS logic, and it was hell trying to keep the jitter down, what with prop delays depending on Vcc and Vcc being whacked by wildly-jumping-around chip supply currents. Never again.

Microstrip is OK since it's just a signal edge we're trying to snapshot. But a 3.3 volt signal with, say, a 3 ns edge is 1 volt/ns, so 20 ps corresponds to a noise level of only 20 millivolts, sort of scairy in this context. Chip ground bounce alone will be more than that. Statistical cheating can result... things like very non-Gaussian jitter patterns.

John

Oh, I see. The errors somewhat cancel out. But still if you don't have a flat bandpass the edge is going to arrive with all kinds of kinky phase and amplitude shifts plus a stretched risetime, not to mention reflections from each discontinuity in the signal path.. Not exactly the best thing to try to trigger on.

Yep, and if the goal is to get random numbers, the noise and reflections could possibly to mess up the stats.

I still think

in particular he is referring to the following:

the power supply usually has lots of capacitance and a closed-loop controller. this makes the PSU look a lot like an ideal voltage source. The interconnect from psu to decoupling cap and chip basically looks like an inductor. so looking back from the IC pin, you see the decoupling network paralleled with the interconnect inductance (the PSU looks like a dead short). This parallel LC combination can (and does) resonate, leading to a high (theoretically infinite) impedance at the parallel resonant frequency.

If you simulate your decoupling network in its entirety, including the psu interconnect inductance and output impedance, you can clearly see this.

Jerold Graeme talks about it in his opamp books.

HTH

Cheers Terry

BTW somebody else chimed in on another thread, about the impossibility of doing fast edge measuremewnts without a multi-layer board:

his is good advice, but while we spent three years getting our prototype working, the interpolation system only needed a month or so of work.

Our biggest single problem was caused by the printed circuit department, who "knew" that the ordering of the inner layers of a printed circuit board didn't matter, so had a six layer board made with the ground planes on layers 3 and 4, rather than 2 and 5 as I'd carefully specified in my release note to the printed circuit department.

It took us months to work out why the board wouldn't work - every time I looked in on the engineer who was working on the board (nominally my boss at that point) I'd point out to him that he had the board layers stacked up wrong in his pile of documentation, but it took about six weeks before he drilled down through the board to check. Once the penny dropped, he sort of got the board working by replacing all the critical tracks with lengths of sub-minature coax (50VMTX, still stocked by Farnell) but we had to get another batch of boards made before we had anything that looked like a prototype.

The two outer layers of the board weren't FR4 epoxy glass, but Teflon cloth bonded with isocynate resin, and the board were biggish - triple extended Eurocards, largely to accomodate mixed DIN41612 connectors with coax inserts - and they cost us about $1500 each. Populating them cost as much again.

Have you looked at their reference design:

This board uses SIX conducting layers. And TWELVE C1210's and TWELVE more 0805's.

Maybe you want to take their hints? :)

I'm in love with you.

In most PCBs they are.

That only works if the ground and power planes are closer together than

This strikes me as more of a management problem than an engineering problem. Based on your post and reading between the lines a little bit, I'm guessing that this is a very low-quantity project. I'm also guessing that you have already provided a cost and perhaps form factor estimate for the project and a schedule for completion. I'm also guessing that since the project is low-quantity that you don't have to worry about safety/EMC, etc.

Anyway, this means that the cost of the capacitors and a board with an additional layer(s) are probably miniscule compared to the cost of the overall project, but exceed your original estimate and you are reluctant to admit your relatively insignificant error. My experience has been that whenever you make a mistake, broadcast it loud and clear to everyone involved and do it as soon as possible and move on. Otherwise, you'll probably wind up amplifying the problem by incurring even more costs and perhaps impacting the schedule.

There's no engineer on this planet, who hasn't had hands-on experience with the circuit, who can tell you if the 47uF caps are necessary with the pico-second rise times. What you need to do is cook-book this circuit, to the extent possible, using the manufacturers application notes and move on. In fact your next priority should be getting as much information as you can on the design of the circuit board. Call the factory and try to talk directly with a design engineer. With low quantities this can be difficult to do, but I would try it anyway.

Max

Where did the 5 mil limit come from? I do picosecond-speed, low-noise stuff on boards with 10, sometimes 15 mil plane spacing, and it sure seems to work.

John

Very interesting problem. You would really enjoy a high speed digital design class taught by Lee Ritchey, "Right The First Time". He talked about a similar stackup problem and how he always adds layer markings to allow him to verify the correct stackup as well as providing a way to directly measure the thickness of the copper. He puts a small stripe along the edge of each layer with the length proportional to the layer. I know we have all been taught that exposed copper is a bad thing, but in reality, this causes no problems since these stripes are not connected to any signals.

As to the teflon, he claimed that there were virtually no situations that actually requires this. It has been a couple of months since I took the class, so I don't recall all the details, but I recall that if you pick a good FR4 type board, you can make it do pretty much anything you want. He builds board with 4 GHz and higher speeds, so I have confidence in his methods.

Where did you get this info? If you just think about that claim, you will realize that it is not very sound. Does a capacitor stop being a capacitor if the plates are more than 5 mil apart? In fact I think you will find that at 5 mil you are getting a *great* decoupling capacitor and at wider spacings you still get very good capacitors with very good high frequency response. Of course the value of the capacitance drops as you widen the spacing, but an 8 mil spacing is not going to "ruin" the effectiveness of the plane decoupling.

This is just the sort of general rule that Lee Ritchey debunks in his class. That was one of the truely impressive aspects of the class, the way he tears apart a lot of the myths that people have developed and never chalenge or verify.

We label each layer, in copper LAYER 1, LAYER 2, etc. Nobody's ever fabbed them wrong.

We do 5 GHz stuff on FR-4, but the distances are very small. Some true microwave stuff, like microstrip filters or physically long structures, could benefit from the lower losses, and sometimes other, more carefully controlled dielectric constants can be handy.

If the copper is given the usual underside black-crud coating to make it stick better to the dielectric, copper losses are bad. Untreated copper on teflon has very low loss, but the copper wants to peel away.

John

When Lee talked about how he did it, I said that simple labeling should be enough, right? Then he told us of a time that the one of his boards came back wrong. He had done everything that needed, including labeling of the layers. But the actual stackup at the fab house is a manual operation where a guy physically drops the layers one on top of another. This time he got it wrong and the boards were all wrong. The only way to tell was if you cut the board open or you had markings on the edges. He had markngs on the edge, so he found the problem quickly.

That was what Lee said. Basically you can do the job without the teflon and it is pretty much impractical to use in a commercial job.

You don't need copper on the edge of a board to check stackup. Just place a number sequence one digit on each layer and leave windows for it on any planes. Look through the board and read 1234.....

Yes, good point, but that uses up a lot of space on the board and tells you nothing about the thickness of the copper and spacing of the stackup. There are any number of problems that can happen in manufacturing. Finding out when the assembled boards dont work is far too late.

Does anyone know the source of the concern with exposed copper on PCBs? It is likely a bad idea on the signals and pads. But why would copper at the edge of a board be a bad idea if it is not touching any signals?

I suppose that could happen, but it hasn't for us, so far. What *is* too common is for the board houses to take huge liberties with the stackups, getting the dielectric thicknesses wrong. I think the safest thing to do is to specify all dielectric thicknesses the same, which they usually get right, and design around that.

Actually, a copper pattern that goes all the way to the edge will verify stack sequencing *and* thickness easily. Except some board houses will call and ask if we really want that, and some will edit our gerbers to pull all the copper away from the edges!

And don't even hope that you'll get 1 oz copper when you call out 1 oz. They usually start with 1/2 or 1/4 oz laminate these days, and plate it up, and quit too soon. I even specify 1 oz with a minimum 700 micro-ohms per square resistivity, and seldom get that!

John

They don't have to be big. They don't even have to be inside the board outline to give the PCB manufacturer a very obvious check he got the stackup right.

Your exposed copper doesn't have to be inside the board outline either if you get boards supplied in a biscuit or get supplied the surrounding scrap. I am a bit dubious about measuring thickness by looking at the edge of the board. Have you ever done it?

I think you would have to grind or rub it down first because the routing will burr and spread the copper. Then you need a decent measuring microscope that you can fit a board into edge on. I suspect it would be more practical to take a sample from outside the board which you can cut down, clean up, and fit in a microscope.

I have. It works fine, if you have the measuring optics.

Not in my experience. The copper layers are nice and sharp.

Edmund has a cheap handheld measuring microscope with a graticule, $50 or something like that, that will resolve 1 mil. It needs a lot of light, but it works.

John