Grin, I did use that nebulous qualifier "sorta". Do you think there is more going on than just heating... getting to some critical temperature? (as you know) Collector heating is spread over a large volume, while avalanching will be be in the small depletion region.
I think I could make a hand-wavy argument that the local temperature in the depletion region would be hotter by the ratio of the volumes...(assuming some kind of planar geometry).
It would be a fun science project.
George H.
I'm pretty sure I recall my real-solid-state-guy colleagues saying that the leakage and beta degradation was due to hot carrier damage, i.e. dislocations and surface states caused by impact from abnormally energetic electrons.
That ought to anneal out just fine, the same way radiation damage does, and for the same reason.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Did you see my post up thread from Aug 12th, even after the first zap of a mere 39uJ I saw degradation so I am sure the effect is not thermal but is electron/hole related.
piglet
The mechanism has been studied already- something to do with high energy electrons (hot carriers- not the FedEx gal) under avalanche conditions.
If you bake the transistor at elevated temperature, the beta increases, so forensics are possible.
--sp
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Thanks, I've mistakenly assumed that "hot carriers" described the electrons that caused the ionization in the avalanche, But it's a surface state thing,,, It's always nice to learn something new.
I saw similar type breakdown when I tired to avalanche a normal photodiode. I saw breakdown, but it had no light intensity dependence. Breaking down around the edges (or something) I figured.
George H.
Yeah I did, but I must have ignored it in my rush for a thermal model.
Thanks again. (I hope it's OK that my method of learning stuff on SED is to say what I think and then get corrected.)
George H.
I think there is damage both in the bulk and at the bottom of the oxide, but I have no idea which is more important.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Yeah, thanks I didn't read that before. (Which is pretty obvious.) Things are more complicated than some simple thermal model.
George H.
The surface of the transistor has B and E metallizations, and is prepped and passivated so that the surface conduction is minimal. But when you reverse-bias the BE junction, you create a field that can move ions around the surface (where bonding is weak). It's called electromigration, and it is likely that it is killing the beta.
Impurities that move into the gap when Vbe is positive or zero are carefully removed during manufacture. Impurities that move into the gap when Vbe is negative are not as well controlled.
Is "die N die" worse than "pick N place"? (DND vs PNP)
You must be buying transistors made with the old-fashioned upright diffusion.
Hell, they even did not make uA709's that way. [except maybe as a special for a monied client, and then damn few parts at that]
There is yet another way to turn off the bottom transistor.. Drive its base via a resistor divider that uses an inverted NPN for base (over-current) bypass. That is a bit sneaky, it uses the base voltage being higher than the input drive to turn it on and pull current (excess base charge) out; the more the charge,the higher the base voltage and the higher the current (can be up to an amp peak for a few hundred picoseconds). This trick can almost completely eliminate* the "normal" supply spike during the low-to-high transition.
(*) invisible for one to 8 devices, but can be seen, sort-of, for 50 TTL gates being driven at the exact same time.
See my earlier posting about use of 2 resistors and an inverted NPN.
Yup; jest what i sed.
People have used PIN diodes in the same sort of way, or else speedup caps. Both help quite a lot.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
"Mid-gap impurities" doesn't refer to physical location, but to the impurity energy levels.
The recombination rate due to an impurity state goes approximately as
1/cosh((E_trap - E_F)/kT), where E_F is the intrinsic Fermi level (i.e. halfway up the gap). (*)That makes mid-gap states exponentially more effective in causing recombination. Obviously this is more important in the base region, where recombination kills the beta.
Electromigration is mostly a problem in metal wiring. Upper level copper wiring shouldn't exceed 10**6 A/cm**2, or 10**5 A/cm**2 for Al. (Buried wires can go a factor of two hotter than that, at least if they're in a solid dielectric like SiO2 or FSG, where the mechanical support slows void formation.)
Cheers
Phil Hobbs
(*) Sze, second edition, eq 59 on P. 37.
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Yes, in discrete designs; i was referring to an IC (gated logic driver).
Yeah, sloppy language on my part. I intended to refer to the surface space between B and E electrodes. Electromigration becomes an issue at high current densities, and Zener breakdown causes the right kind of current distribution to do that near the silicon/oxide interface. Any dirt on the surface can join the migration...
At least these are already SMT :-)
-- Regards, Joerg http://www.analogconsultants.com/
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