We are looking to use a Varitronix MLDS16166 display on a device. Looking at what passes for a datasheet, the contrast adjust Vlcd (aka V0) shows what appears to be a requirement that it be delayed 50 ms after Vdd for the controller logic. However, I can't find that requirement in the controller documentation, nor do any of the application notes (even from Varitronix) show such a delay - they just drive Vlcd from a voltage divider (variable) off of Vdd.
Now I can put in the power supply sequence if I have to... just some extra components and board space that I would rather use for something more important. So does anyone know if this delay is really required? [Why spec it if it isn't, but then why never show the delay in any of the application notes if it is?]
tnx, jmk
----------------------------------------------- James M. Knox TriSoft ph 512-385-0316
1300 Koenig Lane West fax 512-371-5716 Suite 200 Austin, Tx 78756 snipped-for-privacy@trisoft.com
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