GAL16V8D pal what does it do ?

Nothing. Until it's programmed, anyway.

Basic way? Depending on how it's programmed, applying certain inputs affects the state of it's outputs.

It's a programamble chip, intended to replace typical 'glue logic'.

If you're trying to fathom what one does in a piece of equipment you're trying to reverse engineer, you're stuck without the programming details.

Graham

hi, thats sorta what im trying to do . what exactly do you mean by the programming details. ?

this is the situation :

i have a eprom for a cars ecu that has been modified for perfromance, and the eprom has been removed from the carrier , and a " pal security board " has been soldered in which contains a GAL 16V8D .and then the eprom plugs on top of the board .

i removed the eprom , read it and burnt it to another , but it wont work ( engine wont run) .

it looks like the eprom wont start the car unless its plugged on to the pal security board, and from what i have found out so far , the , eprom looks for teh security board every so often and if it aint there the car wont run.

any body know how i can go about modifying the data so teh car will run without the pal board ? any links, ideas etc...

thanks,

mark k

"mark krawczuk" wrote in news:468d0e11$0$41303$ snipped-for-privacy@lon-reader.news.telstra.net:

Short answer, buy another security board form the vendor you obtained the first from. They are using the PAL to protect their copyright to the modified code therein.

at $280 for each board , i think not . the whole setup to tune your car about $1400 plus , u buy the equipment , u do the tuning and u still have to spend $280 EACH time u want to tune a car , EVEN THOUGH u OWN the tuning hardware. mark k

Crude, short answer: it's a tree (or grid, or array) of logic AND's and OR's, which can be programmed as to where the AND's and the OR's are connected between inputs and outputs.

A GAL is a programmable logic circuit. Several (N)ANDs (N=ORs can be simply replaced by one single circuit, saving place, supply current, and, additionally, it makes it more flexible.

I have used a GAL16V8 for address decoding logic in a single board system:

----------------- ROM RAM LCD DIN1 DIN2 DOUT1 DOUT2 /AHH X x 1 1 1 1 1 /AHL X x 1 1 1 1 1 /PSEN 0 1 1 1 1 1 1 A7 A A 1 1 1 1 1 A6 A A 1 1 1 1 1 A5 A A 1 1 1 1 1 A4 A A 1 1 1 1 1 A3 A A 0 1 0 1 0 A2 A A 0 0 1 0 1 /RD 0 X X 0 0 x x /WR X X X X x 0 0 Resulting Range From 0x0000 0x0000 0xFFF0 0xFFF8 0xFFF4 0xFFF8 0xFFF4 To 0xFFFF 07FEF 0xFFF3 0xFFFC 0xFFF7 0xFFFC 0xFFF7

-----------------

This follows to a boolean algebra like this:

-----------------

lcden = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * /a2 * /wr + psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * /a2 * /rd

/din1 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * /a2 * /rd

dout1 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * /a2 * /wr

/din2 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * a2 * /rd

dout2 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * a2 * /wr

/csrom = /psen * /rd

/csram = psen * /rd * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * a2 + psen * /wr * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * a2

-----------------

Finally the programming of these ANDs and ORs can be made with a text editor, a GAL ASM compiler translating the logic needs into a programmable file. Finally u put this file with a GAL programmer into the circuit. title ADDRESS DECODER V2 pattern MOGAv10a revision A author Heinz Liebhart company private date 05/01/1999

chip MOGAv10a GAL16V8

;pin 1 2 3 4 5 6 7

8 9 10

; IN IN IN IN IN IN IN IN IN SUPPLY

ahh ahl a7 a6 a5 a4 a3 a2 rd gnd

;pin 11 12 13 14 15 16 17

18 19 20

; IN IN OUT OUT OUT OUT OUT OUT OUT SUPPLY

psen wr lcden din1 din2 dout1 dout2 csram csrom vcc equations lcden = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * /a2 * /wr + psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * /a2 * /rd /din1 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * /a2 * /rd dout1 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * /a2 * /wr /din2 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * a2 * /rd dout2 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * a2 * /wr /csrom = /psen * /rd /csram = psen * /rd * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * a2 + psen * /wr * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * a2

-----------------

Aaah, we already know this equations ;-)

The GAL ASM "compiler" is producing a jedec file for programming the chip and a log file, which e.g. looks like that:

-----------------

EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) Copyright (R) National Semiconductor Corporation 1990,1991 Document file for MOGAv10a.eqn Device: 16V8

$LABELS 20 ahh ahl a7 a6 a5 a4 a3 a2 rd gnd psen wr lcden din1 din2 dout1 dout2 csram csrom vcc

Pin Label Type

--- ----- ----

1 ahh com input 2 ahl com input 3 a7 com input 4 a6 com input 5 a5 com input 6 a4 com input 7 a3 com input 8 a2 com input 9 rd com input 10 gnd ground pin 11 psen com input 12 wr com input 13 lcden pos,com output 14 din1 neg,com output 15 din2 neg,com output 16 dout1 pos,com output 17 dout2 pos,com output 18 csram neg,com output 19 csrom neg,com output 20 vcc power pin

EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) Copyright (R) National Semiconductor Corporation 1990,1991

Device Utilization:

No of dedicated inputs used : 10/10 (100.0%) No of feedbacks used as dedicated inputs : 1/6 (16.7%) No of dedicated outputs used : 2/2 (100.0%) No of feedbacks used as dedicated outputs : 5/6 (83.3%)

------------------------------------------ Pin Label Terms Usage ------------------------------------------ 19 csrom 1/8 (12.5%) 18 csram 2/8 (25.0%) 17 dout2 1/8 (12.5%) 16 dout1 1/8 (12.5%) 15 din2 1/8 (12.5%) 14 din1 1/8 (12.5%) 13 lcden 2/8 (25.0%) ------------------------------------------ Total 9/64 (14.1%) ------------------------------------------

EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)

Copyright (R) National Semiconductor Corporation 1990,1991 Chip diagram (DIP) ._____ _____. | \__/ | ahh | 1 20 | vcc ahl | 2 19 | csrom a7 | 3 18 | csram a6 | 4 17 | dout2 a5 | 5 16 | dout1 a4 | 6 15 | din2 a3 | 7 14 | din1 a2 | 8 13 | lcden rd | 9 12 | wr gnd | 10 11 | psen |______________|

-----------------

Finally this means for your (reverse) engineering:

- Find out which pins are input, which are output.

- Check which in combinations can occur.

- Check the out values for these in. Then you can do your reverse engineering. A simple binary counter connected to the inpus might be useful ;-)

Hope this helps, Heinz

"mark krawczuk" wrote in news:468d7055$0$36722$ snipped-for-privacy@lon-reader.news.telstra.net:

Its called software licensing. Their terms are you pay them $280 per car to use their tuning hardware. The PAL is just there to protect their right to that $280 per car.

Its programmable logic .

Today , it can pck up the stuff not in

the ARM cpu's , such as ultra H.S.

serial to parallel "path" into the cpu .

You can use another cpu , cause they

dont have the serial inputs , a PLD has .

PLDs can do many RLL serial streams

in parallel , CPU's can't .

Some CPU's have USB 2.0 Hi-Speed , which

is Run-Length-Limited , but only one channel .

PLD's can also preprocess the serial , to

allow the CPU to read 1 32 bit word of priorty

info , alllowing CPU to switch tasks quicker .

This 32bit can be the address into the routines .

Thus the PLD is actually redirecting the flow .

.

hi , no u dont pay the money each time to use their tuning hardware , cause u already have to buy the tuning hardware at a cost of $1000 !!! then u have to pay the 280 $