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suggestions on my pcb design..

I need to design a miniature rigid pcb that will have a silcon die wirebonded to it and then take the signals out of this board using a flex cable to a 4in x 4in 4-layer rigid FR4 board (I have already designed this big board and laid out except for the signals coming in from the flex cable). at the bigger board end I intend to have a ZIF connector for the flex cable. There are 20 signals that the flex cable need to carry. My question is,

there are differential signals coming out from the smaller pcb, they must be routed together right ? i know they must be placed close to each other and maintain some distance from other signals. but the problem is i am using 3 mil traces and they are separated by 3 mils ( because of the restriction on the size of the board). so i can have other signals at 3 mils from the differential signals....how do i take care of this ?

i am thinking of using a flex cable to take out the signals. does this usually need to have all the signals on one layer ( I know there is rigid-flex board but i heard its very expensive )

what about the impedance mismatch, since i will be routing the signals at 10 mils on the bigger board...

i am having power and ground signals brought in through the flex cable. i can and should provide a solid ground plane. but the traces that carry the power to the pads i cant make them more than 5 mils. how do i overcome this coz there will be a voltage drop. the supply current drawn is aroun 30 mA. please provide any suggestions..thanks !

Reply to
TD
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1) The chip can be directly placed on the flex; an area around the chip would be restrained from bending by some mounting method. Better yet, buy the IC in standard package as the total cost may be less than 100K minimum and up quantity requirements for the chip; the package does the strain relief. 2) One could use 2-sided flex where ground and power "planes" are used to help decrease inter-trace coupling and lower the impedance *and* decrease the power IR drops. I say "planes" in that wide strips would be used on the back side; obviously the whole side would not be at one voltage level (ground,+5V, etc). They can be bypassed with chip capacitors mounted on the flex: +5 to gnd; gnd to -5 (reading left to center to right). I have seen this trick used before. You mentioned IR drop; the above trick would help that and help matching if there are signal reflection concerns.

Another way is to run the +sig on the top and the -sig on the bottom, which keeps the differential E-field close to the 3-mil stripes and severely reduces coupling to nearby stripes. In addition, the nearby stripes could be (bypassed) power or ground stripes; killing any coupling elsewhere. That means a given power or ground is carried by multiple stripes, thereby reducing the IR drop by a large fator.

You did not say how many hundred of feet long the flex would be.

Reply to
Robert Baer

thanks for your reply. i also thought about going for double sided flex printed circuit with a solid ground plane or like you said wide strips for power/ground. but the traces leading into the pads on the top layer are going to be run at 5 mils( i do not have an option here !)

1) The chip can be directly placed on the flex; an area around the chip

would be restrained from bending by some mounting method. Better yet, buy the IC in standard package as the total cost may be less than 100K minimum and up quantity requirements for the chip; the package does the strain relief.

We have to use the silicon die because the board with die has to be placed inside a box and hence its dimension has to be max 3mm x 10mm. couple of companies i talked with were willing to do this as flex printed circuit. now is the wirebonding to FPC and the stiffness of it an issue or is it generally followed practice.

the signals are differential signals and will run max at 15-20MHz. And I am trying to use a flex cable or a flex circuit that will be

1-2inches long !
Reply to
TD

we decided it is going to be a double sided Flex printed circuit and chip-on-a-flex with FR4 stiffner at chip location seems to good. and i should have a ground/power plane at the bottom layer.

Reply to
TD

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