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'Subcircuit levels', and LTspice...

Hello. I might have missed something obvious but I'm usually good with adapting subcircuits to LTspice, making my own symbol files, etc, but this extra-levels problem is new and beats me...

The LOG112 log amp subcircuit from Texas Instruments uses more than one level of subcircuit in a single file (Two subcircuits on that second level, it seems, each with 5 pins). LTspice finds this file from my symbol file, but announces that the XU1 instance has more pins than the subcircuit. This is not true. :) BUT, the two sub-subcircuits in the file have 5 pins, which might have something to do with this. I tried a crude omission of those sub- subcircuits to see if it at least stopped claiming pin count errors, and it didn't.

Instead of blundering further I'll just ask up front: can anyone bail me out of this with an explanation of what to do to make the TI subcircuit work in LTspice if LTspice can't use this extra-level method?

Complete unedited TI subcircuit file follows... (I can add my symbol file but I promise you it has a matching pin count for the first uncommented line in the following data. The values, and order, are also the same.)

  • BEGIN MODEL LOG112
  • BEGIN NOTES
  • THIS MODEL USES TWO SUBCIRCUIT LEVELS, IE THE
  • LOG112 SUBCIRCUIT IS ONE LEVEL AND THERE IS
  • ONE ADDITIONAL LEVEL INSIDE THAT SUBCIRCUIT.
  • ONE COMPONENT (R2) HAS DIFFERENT SYNTAX FOR
  • DIFFERENT SIMULATORS - SEE R2 BELOW.
  • MODEL FUNCTIONAL TEMPERATURE RANGE IS -40 TO 85 C.
  • HIGH ACCURACY TEMPERATURE RANGE IS -5 TO 75 C.
  • NOT ALL PARAMETERS TRACK WITH TEMPERATURE.
  • CONVERGANCE, DC SWEEPS, AND TIME DOMAIN ANALYSIS
  • WILL USUALLY REQUIRE SETTING ANALYSIS OPTIONS
  • SUCH AS ITL1, ITL2, AND ITL4 RESPECTIVELY.
  • CONVERGANCE CAN ALSO BE ENHANCED BY USING
  • NODESET TO SET THE OUTPUT NODE (VLOG) AND
  • OR THE AUX AMP OUTPUT NODE (VO3).
  • FOR ACCURATE RESULTS AT INPUT CURRENTS BELOW
  • ONE NANAOAMP SET GMIN TO 3E-13.
  • END NOTES
  • BEGIN FEATURES
  • SUPPORTS DC, AC, TRANSIENT, AND NOISE ANALYSIS.
  • LOGGING AND AUXILIARY AMPLIFIERS ARE MACROMODELS
  • WITH THE FOLLOWING FEATURES:
  • OPEN LOOP GAIN AND PHASE, CMRR W FREQ EFFECTS,
  • PSRR W FREQ EFFECTS, INPUT VOLTAGE AND CURRENT
  • NOISE W FREQ EFFECTS, INPUT BIAS CURRENT AND
  • INPUT CLAMPS, OUTPUT CLAMPS, INPUT CAPACITANCE,
  • OUTPUT SWING VS IO, OUTPUT CURRENT THRU THE
  • SUPPLIES, SLEW RATE, CURRENT LIMIT, AND INPUT
  • COMMON MODE RANGE.
  • LOGGING TRANSISTORS HAVE NON-IDEAL PARAMETERS.
  • LOGGING TRANSISTORS HAVE NOISE EFFECTS.
  • LOG CONFORMITY ERRORS ARE MODELED.
  • TEMPERATURE EFFECTS OF LOG ERRORS ARE MODELED.
  • TEMPERATURE EFFECT OF GAIN ERROR IS MODELED.
  • BANDWIDTH AND DYNAMICS ARE REALISTIC.
  • COMPENSATION IS REALISTIC.
  • UPPER LIMIT ON I1+I2 AT LOW VCC IS MODELED.
  • NOTE THAT THE INTERNAL REFERENCE IS MODELED
  • AS A SIMPLE VOLTAGE SOURCE WITH NO DEPEND-
  • ENCE ON SUPPLY, NO DRIFT, NO OUTPUT IMPEDANCE,
  • AND NO DYNAMIC FEATURES.
  • END FEATURES
*
  • PINOUT ORDER I1 +IN -IN VLOG V+ VO3 VREF V- GND REFGND VCM I2
  • PINOUT ORDER 1 3 4 5 6 7 8 9 10 11 13 14 .SUBCKT LOG112 1 3 4 5 6 7 8 9 10 11 13 14 X1 13 14 6 9 5 LA112 R1 15 5 1567.4
  • PSPICE AND PSPICE DERIVED SYNTAX FOR R2 R2 10 15 212 TC1=3.78M
  • END PSPICE SYNTAX R2
  • BERKELEY 3X.X SYNTAX FOR R2
*R2 10 15 212 R2M *.MODEL R2M R TC1=3.78M
  • END BERKELEY SYNTAX R2 Q1 16 15 17 QL112 Q2 18 10 17 QL112 X2 13 1 6 9 19 LA112 R5 0 14 1E12 R6 0 1 1E12 R7 17 19 600 C1 1 19 180E-12 R9 17 16 1E12 R10 18 17 1E12 R11 14 18 92 R12 16 1 92 D1 17 15 DS D2 17 10 DS X3 3 4 6 9 7 AA112 V4 8 11 2.5 R15 11 8 1E12 IQA 6 9 0.63E-3 .MODEL DS D IS=1E-18 RS=10 CJO=1E-12 TT=5N .MODEL QL112 NPN BF=440 IS=1E-15 NF=1 EG=1.2056
  • ISE=1E-17 NE=1.5 ISC=1E-17 NC=1.5 VAF=125
  • RB=49 RBM=2.65 IRB=60E-6 RE=0.0404
  • IKF=0.06 CJE=12.2E-12 VJE=0.77 MJE=0.3
  • CJC=1.5E-12 VJC=0.64 MJC=0.425 XCJC=1 FC=0
  • TF=300E-12 XTF=1 VTF=0 ITF=0.01 PTF=5
  • ITF=10E-3 TR=1E-6 CJS=55E-12 MJS=0.5 VJS=0.58
  • XTI=2.3 XTB=1.5 NR=1 KF=1.6E-16 AF=1 .ENDS .SUBCKT LA112 3 2 7 4 6 C00 6 0 0.1E-12 Q26 8 9 10 QON Q27 11 9 12 QOP Q28 4 13 14 QOP Q29 7 15 16 QON I4 8 15 110E-6 I5 13 11 110E-6 R35 14 17 1 C6 18 19 60E-12 R36 19 18 1K G1 18 19 20 0 -1E-3 G2 21 19 22 23 -900E-6 R37 19 21 1E10 C7 20 24 30E-12 R38 20 21 8E3 E1 25 19 20 19 1 D2 25 21 DD R39 19 24 1.5E3 R41 26 23 300 R42 26 22 300 V7 27 11 0.65 R47 6 17 50 D1 26 27 DD D3 21 25 DD D4 28 8 DD D5 11 29 DD V8 28 21 1.3 V9 21 29 0.9 E6 30 0 8 0 1 E7 31 0 11 0 1 E8 32 0 33 0 1 R48 30 34 1E4 R49 31 35 1E4 R50 32 36 1E4 R51 0 34 1 R52 0 35 1 R53 0 36 1 E11 37 38 36 0 0.03 R54 39 33 1E3 R55 33 40 1E3 C10 30 34 0.5E-6 C11 31 35 100E-9 C12 32 36 1E-12 E12 41 37 35 0 0.025 E13 42 41 34 0 0.1 R60 41 42 1E9 R61 37 41 1E9 R62 38 37 1E9 E22 39 0 2 0 1 E23 40 0 42 0 1 E24 43 44 45 46 0.067 I7 0 46 100E-6 D6 46 0 DVN I8 0 45 100E-6 D7 45 0 DVN E25 11 0 4 0 1 E26 8 0 7 0 1 I9 7 4 342E-6 R65 4 7 400E3 E27 19 0 8 11 0.001 C13 2 0 2E-12 C14 42 0 2E-12 C15 42 2 1E-12 V10 44 2 0 R34 12 15 1 R67 13 10 1 R68 17 16 1 I13 42 0 4E-12 I14 2 0 4E-12 J1 22 47 48 JIP J2 23 49 50 JIP R72 50 51 100 R73 48 51 100 Q30 52 52 53 QIP R74 53 54 220 R75 55 54 220 Q31 51 52 55 QIP V12 8 54 3.5 I15 52 11 230E-6 V13 49 42 0 C17 9 19 30E-12 R76 19 9 1K G3 9 19 18 19 -1E-3 I16 0 56 100E-6 D8 56 0 DIN I17 0 57 100E-6 D9 57 0 DIN G4 2 42 57 56 1E-6 E29 58 0 57 56 230 R77 0 58 220 C18 58 49 1E-12 C19 58 47 1E-12 R81 38 3 400 R82 43 47 400 J3 8 49 8 JIN J4 8 47 8 JIN J5 47 11 47 JIN J6 49 11 49 JIN D10 6 7 DD D11 4 6 DD .MODEL DVN D KF=1.6E-13 .MODEL DIN D .MODEL DD D .MODEL QIP PNP .MODEL QON NPN BF=164 RC=175 .MODEL QOP PNP BF=164 RC=175 .MODEL JIP PJF BETA=1.5E-3 IS=1E-14 .MODEL JIN NJF IS=1E-18 .ENDS .SUBCKT AA112 3 2 7 4 6 C00 6 0 0.1E-12 Q26 8 9 10 QON Q27 11 9 12 QOP Q28 4 13 14 QOP Q29 7 15 16 QON I4 8 15 50E-6 I5 13 11 50E-6 R35 14 17 1 C6 18 19 120E-12 R36 19 18 1K G1 18 19 20 0 -1E-3 G2 20 19 21 22 -900E-6 R37 19 20 1.25E8 C7 20 23 30E-12 R39 19 23 3E3 R41 24 22 300 R42 24 21 300 V7 25 11 -0.32 R47 6 17 50 D1 24 25 DD D4 26 8 DD D5 11 27 DD V8 26 28 1.25 V9 29 27 0.6 E6 30 0 8 0 1 E7 31 0 11 0 1 E8 32 0 33 0 1 R48 30 34 1E4 R49 31 35 1E4 R50 32 36 1E4 R51 0 34 1 R52 0 35 1 R53 0 36 1 E11 37 38 36 0 0.15 R54 39 33 1E3 R55 33 40 1E3 C10 30 34 1E-6 C11 31 41 1E-6 C12 32 36 1E-12 E12 42 37 35 0 0.2 E13 43 42 34 0 0.1 R60 42 43 1E9 R61 37 42 1E9 R62 38 37 1E9 E22 39 0 2 0 1 E23 40 0 43 0 1 E24 44 45 46 47 0.036 I7 0 47 100E-6 D6 47 0 DVN I8 0 46 100E-6 D7 46 0 DVN E25 11 0 4 0 1 E26 8 0 7 0 1 I9 7 4 103.8E-6 R65 4 7 606E3 E27 19 0 8 11 0.001 C13 2 0 2E-12 C14 43 0 2E-12 C15 43 2 4E-12 R34 12 15 1 R67 13 10 1 R68 17 16 1 I13 43 0 5E-12 I14 2 0 5E-12 R72 48 49 100 R73 50 49 100 Q30 51 51 52 QCP R74 52 53 220 R75 54 53 220 Q31 49 51 54 QCP V12 8 53 1.05 I15 51 11 60E-6 V13 55 43 0 C17 9 19 33E-12 R76 19 9 1E3 G3 9 19 18 19 -1E-3 I16 0 56 100E-6 D8 56 0 DIN I17 0 57 100E-6 D9 57 0 DIN G4 2 43 57 56 1E-6 R81 38 3 400 R82 44 58 400 J3 8 55 8 JIN J4 8 58 8 JIN J5 58 11 58 JIN J6 55 11 55 JIN D10 6 7 DD D11 4 6 DD Q32 22 55 48 QIP Q33 21 58 50 QIP E30 28 20 59 0 1.1 E31 20 29 59 0 1.2 I18 0 60 1E-4 D12 60 0 DD V17 59 60 -0.6 R87 0 59 1E9 E32 45 2 61 0 1 R88 61 0 4.2E4 C20 61 0 0.1E-12 R90 41 35 20 C21 41 35 0.1E-6 .MODEL DVN D KF=1.6E-13 .MODEL DIN D KF=1E-14 .MODEL DD D .MODEL QCP PNP .MODEL QIP PNP BF=2650 .MODEL QON NPN BF=80 RC=950 .MODEL QOP PNP BF=200 RC=175 .MODEL JIP PJF BETA=1.5E-3 .MODEL JIN NJF IS=1E-18 .ENDS
  • END MODEL LOG112
Reply to
Lostgallifreyan
Loading thread data ...

Put this all inside a .LIB declaration, then have your symbol call

X 1 3 4 5 6 7 8 9 10 11 13 14 LOG112

That's the way it would be done in PSpice.

(I'm guessing that an LTspice "symbol file" can't cope with nesting.) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Jim Thompson wrote in news: snipped-for-privacy@4ax.com:

Fast! Thanks, I'll explore that (and any other gotchas you or anyone can think of). Would the .LIB be a useful catch-all element in this context like a in HTML? If so that could be very useful.

I did find what looks like AN answer, if not THE answer... (Is why I'm back so soon..) Turns out my perfect match for symbol pins with subcircuit pins was a problem, the symbol file will not accept gaps! So I renumbered contiguously for 1 through 12 and the next runtime error I saw was the expected one considering I hadn't wired up the model yet. :) I'll do that later or tommorow to see if this is now complete, but I'm interested in any advice about the implications of subcircuit 'levels' in one file because I couldn't find (via Google) anything even allusive, never mind definitive, about them. I know so little about them that I couldn't find a reliable way to search.

Reply to
Lostgallifreyan

Possibly. I regularly import netlists straight from PSpice into LTspice, with all my models collected in .LIB files (*). So far I've not had a hitch.

(*) In my darker past ;-) I've made multi-line symbols. In PSpice you can declare that multi-line symbols are to be treated as subcircuits or not... given me some grief. In my "spare" time I need to go back and clean up the resulting mess and leave only multi-line symbols as NOT subcircuits, like my LoopGain mechanism.

That's odd, PSpice has no problem with extra white space on a single line.

...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Jim Thompson wrote in news: snipped-for-privacy@4ax.com:

Gaps as in not 1 3 4 5 6 7 8 9 10 11 13 14. :) Those are fine in the model file, but not the symbol, and aren't on one line there either.. While these numbers for subcircuit pins must match one to one in the model (as literal names, I think), it wasn't true for the .ASY file, which needed its pins renumbered contiguously from 1. I think all it cares about is that, a matching count, and perhaps a correct order though I wouldn't have a reason to order the numbers any other way.

As there is only one main subcircuit in the model file, I omitted the "SYMATTR SpiceModel LOG112" and left the "SYMATTR ModelFile LOG112.sub" intact so there was no way to accidentally select the sub-subcircuits in the part editor dialog in a schematic. I did a deliberate test of that to see if it invoked the pin count error because I expected it to (it did), so I'm hoping that next time it will not only see the main subcircuit, but that the internal referencing in the TI file for LOG112 will work in LTspice without editing. If not I'll explore .lib as a way to 'bracket' those two sub- subcircuits.

I'll test this properly tomorrow, I'm currently taking a break from watching Mister Wint and Mister Kidd commit unspeakable indignities on Mister Bond's person..

Reply to
Lostgallifreyan

;-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Lostgallifreyan wrote in news:Xns9F8295986AD0zoodlewurdle@216.196.109.145:

Just posting in case anyone comes this way and wonders about it... it works now, the two second-level subcircuits in the .MOD (renamed .sub for LTspice) are seen correctly without any editing in that file. With the SYMATTR lines as decribed above (one included, one omitted), in the .asy symbol file, it works (and avoids a risk of selecting one of those sub-subcircuits by mistake) provided that the 12 connected pins of the 14 pin package are contigously numbered (1~12) in the right order instead of matching exactly the subcircuit pin numbers.

My own circuit isn't yet behaving quite as I want it, but that's because I do know the log amp IS now working. :) I got a linear output from an exponential input, clearly impossible otherwise.

Reply to
Lostgallifreyan

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