Re: Great Movie Line from an Old Bob Hope Movie

"Helmut Sennewald" wrote in news:cfblg8$2rr $05$ snipped-for-privacy@news.t-online.com:

Thanks a lot Helmut

Paul

It's in this list of app notes:

...Jim Thompson

=_NextPart_001_0024_01C47FD5.83DDA880 Content-Type: text/plain; charset="windows-1251" Content-Transfer-Encoding: quoted-printable

BlankHi, everybody. Could someone help me to translate Allegro PCB to = ADS to simulate a it there? I started to work with Cadence 15.0 and I am = surprised: I can't translate pins to DXF. (it worked in the previous = version no problems) I use Allegro>export>DXF to create DXF file. = Ichecked and unchecked "translate padstacks as blocks" but no pins = appeared... Thanks in advance.

The article below shows a good method to measure the S-parameters using Micro-Cap. It should work with any simulation programme.

mehran

kubik wrote: : I need to use a circuit simulator under a linux O.S. I downloaded LTSpice : ( Switcher-CAD III ) and i found a .exe file. : I ask: is there a linux version of LTSpice? : If not can i use LTSpice under wine and how i can do it?

LTSpice is wonderful & runs well under wine, as has already been pointed out.

Since you are a Linux dude, you might want to check out ngspice, which is a Linux-native, open-source version of classic SPICE 3f5:

Grab the 15fixedRC2 version.

It is a "work in progress", meaning that it sometimes won't converge when LTSpice will, and very occasionally exhibits other quirks. Personally, I find it extremely useful as a complement to LTSpice, particularly because I sometimes want to use a CLI interface to SPICE, which LTSpice lacks (or I haven't found yet).

Stuart

That is not the recommended one. In fact the rule to give parameter to your awk (gawk/nawk) command depend of your OS and your version of awk (be carefull, lot of time now awk is an alias fot gawk)

If you want just use the name of you input file into your awk command script you can use the predefined parameter FILENAME, like this

awk '--- FILENAME ---{---}' $1

as you can use IFS, OFS, BEGIN, END...

If you want more parameters, look your 'man awk' result and check if your awk is not GNU awk (gawk)

Regards, JaI

Many thanks, Mehran. That's just the kind of info I'd be trawling the 'net for and been unable to find.

Regards, Paul

Stuart Brorson's info is within the message at location sci.electronics.cad:

You can write netlists, save with .cir extensions and load them on LTspice. I've used this to put netlists made by other simulators, in LTSpice.

Hello, at present I am working on an Infiniband implementation on a Virtex-II Pro. As far as I know the build-in RocketIOs are fully compliant to the Infiniband standard (beacon and variant CRC excluded). There are two types of CRC, the invariant and the variant type. Although the RocketIOs are able to calculate at least one type, i.e. the invariant CRC, you cannot make use of it in this particular case. The reason for this is that the invariant CRC is needed for the variant CRC type which you have to handle yourself, anyway. Has anyone ever tried or finished an Infiniband implementation inside the V2P/RocketIOs and could share his experience with me? Or is there any example implementation for the whole CRC calculation inside the FPGA fabric available? I wonder how one could ever reach the typical 2.5 Gbit/s Infiniband transmission rate when almost all functions must be handled inside the FPGA fabric? Still some other questions: Could someone please help me on the question how often the beacon signal should be repeated before synchronisation is sufficiently established? And what about the packet generation? There are several IBA packet structures. If I assume a plain point-to-point connection it surely would not be necessary to include all that global routing stuff inside the header. So what would be the adequate format to use? The "local packet" structure or maybe just "raw packets"? If someone got the slightest clue, please post a write an email! Any answer is appreciated. Best regards, Bruce

Keywords: FPGA, Xilinx, Virtex 2, Virtex2, Virtex-2, Virtex II, VirtexII, Virtex-II, RocketIO, RocketI/O, RocketIOs, RocketI/Os, Rocket IO, Rocket I/O, Rocket IOs, Rocket I/Os, Virtex2Pro, VirtexIIPro, MGT, SerDes, Gigabit Transmission, Infiniband, Beacon Signal, Synchronisation, Gbit, Gb, Gbit/s, Gbits, Gb/s, Gbs, P2P, IBA

Hi guys,

Anyone got a spice model, datasheet or both for the BFG194?

Thanks,

p.

Hi

I'm using Cadint to design and Specctra 9.0 to auto-route.

My problem: Specctra think all holes are plated, even though they are set as Unplated in Cadint. I unfortunatly can not make plated holes in my PCB's.

How can I force Specctra *not* to route through holes, only through vias?

Thank you Nils Emil P. Larsen

-- My reply-address is valid.

Hi! does anyone know what OFF SHEET AT ... in protel DXP mean ?

I want to solve this problem.

Thanks

Michele Bergo wrote: : Hi! : does anyone know what OFF SHEET AT ... in protel DXP mean ?

It sounds like you have a stray component placed way, way, way far away from your design area. Try to zoom way out and see if you can find it.

Stuart

"Paul Burridge" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

Hello Paul, the datasheet is on the Infineon website.

I recommend to think of the BFG194 as a three times the chip area BFT192 in a SOT223 package. The datasheets of both transistors really look very similar, except the three times current and capacitances. The SPICE model for the BFT92 is in the datasheet and on the Infineon website. The package models are also there.

The proposed model is a subcircuit. Thus it requires a subcircuit symbol in LTSPICE. You can either modify the standard transistor symbol to become a subcircuit symbol or you use the universal xpnp.asy symbol.

Best regards, Helmut

• A possible SPICE model
• Helmut Sennewald
• Guess: BFG94=3*BFT92(chip)+SOT223

• Pin-Order C B E ..SUBCKT BFG194 200 100 300
• Size -----> 3 times Q1 2 1 3 T389 3 LBI 1 10 0.57nH ; LBI LEI 3 30 0.64nH ; LEI CCB 10 20 14fF ; CCB CCE 20 30 271fF ; CCE CBE 30 10 187fF ; CBE CB 1 3 197fF ; CB CC 2 3 296fF ; CC LBO 10 100 0.84nH ; LBO LCO 20 200 0.15nH ; LCO LEO 30 300 0nH ; LEO ..ENDS

The source:

• SIEMENS Small Signal Semiconductors
• RF-PACKAGE EQUIVALENT CIRCUIT (COMPACT SOFTWARE SYNTAX)
• VALID UP TO 6 GHZ
• >>> SOT223-3 > T389

"Helmut Sennewald" schrieb im Newsbeitrag news:cfj9st$31r$00$ snipped-for-privacy@news.t-online.com...

Hello Paul, there has been a missing inductor in my subcircuit and I have changed one inductor from 0 to 0.001nH. A test circuit file should be already in your email when you read this.

Best regards, Helmut

• A possible SPICE model
• Helmut Sennewald
• Guess: BFG94=3*BFT92(chip)+SOT223

• Pin-Order C B E ..SUBCKT BFG194 200 100 300
• Size -----> 3 times Q1 2 1 3 T389 3 LBI 1 10 0.57nH ; LBI LCI 2 20 1.01nH ; LCI LEI 3 30 0.64nH ; LEI CCB 10 20 14fF ; CCB CCE 20 30 271fF ; CCE CBE 30 10 187fF ; CBE CB 1 3 197fF ; CB CC 2 3 296fF ; CC LBO 10 100 0.84nH ; LBO LCO 20 200 0.15nH ; LCO LEO 30 300 0.001nH ; LEO ..ENDS

• BFT92 Chip

• SIEMENS Small Signal Semiconductors
• GUMMEL-POON MODEL CHIP PARAMETERS IN SPICE 2G6 SYNTAX
• VALID UP TO 6 GHZ
• >>> T389

An LTSPICE symbol for any PNP transistor subcircuit "XPNP.ASY" . Put this symbol into your project (working) directory. You can add it then with the LTSPICE add "Component" menu. The subcircuit definition must be addd directly or via an include file (.INCLUDE filename) to the schematic.

Version 4 SymbolType CELL LINE Normal 16 64 44 76 LINE Normal 44 76 36 84 LINE Normal 16 64 36 84 LINE Normal 40 80 64 96 LINE Normal 16 80 16 16 LINE Normal 16 32 64 0 LINE Normal 16 48 0 48 WINDOW 0 64 24 Left 0 WINDOW 3 64 71 Left 0 SYMATTR Value X-PNP SYMATTR Prefix X SYMATTR Description Bipolar PNP transistor subcircuit PIN 64 0 NONE 0 PINATTR PinName C PINATTR SpiceOrder 1 PIN 0 48 NONE 0 PINATTR PinName B PINATTR SpiceOrder 2 PIN 64 96 NONE 0 PINATTR PinName E PINATTR SpiceOrder 3

I've been trying to look up IC design and can't quite find what i'm looking for.

I want to know what the shapes look like for transistors and such when they are drawn in preparation for being transferred to silicon.

I found one site that showed a cell design:

But this doesn't show the individual components. I know this stuff isn't done by hand anymore but I'd really like to see the shapes of each component. Can anyone point me in the right direction here?

Thank you...

Hello...

I am trying to use a "complex hierarchy" to avoid drawing the same circuit 16 times (namely, a card-edge connector and some glue).

To be specific, every four slots share one 4066 and one 7408, so I have four almost-identical pages in separate folders, so that sheet Slot-A has U1, U2A and U3A, Slot-B has U1, U2B and U3B, and so on.

Then another sheet is meant to have 16 hierarchicals blocks, each implemented successively as Slot-A,Slot-B,Slot-C,Slot-D,Slot-A... wired together with buses and wires.

Using just one such block works fine, but as soon as I add Slot-B I get DRC errors about "same pin connected to two nets" (MNL0031).

On the other hand, the OrCAD docs point out that parts with attached schematics are easier to reuse. Is this what I should be using for my blocks?

BTW, where is the reference for these MNLxxxx errors?

Thanks in advance...

- ariel

Hello

Thank you very much for the quick reply.

Adding a Keepout Router-polygon around each pin/hole not accessible for soldering will effectivly prevent Specctra from using the pins as vias.

Nils Emil P. Larsen

-- My reply-address is valid.

try telling specctra the board is single side or place keepouts either side of pins on the top layer