Hi.
I currently simulate digital ECL circuits using ideal parts from "dig_prim.olb". I put a DELAY on each gate's output to simulate the propagation delay. This is important because the propagation delays are in the dimension of a clock cycle.
Is anyone out there who also uses PSpice to simulate ECL circuits? Does anyone know a more appropriate way therefor? Fore example the availability of true ECL models?
Regards, Norbert
Last time I looked there was an ECL library, so, yes, there are true ECL libraries available. I never did that much simulation with them though, although they are included in the digio.lib, and they took great pains (and it was painful!) to make the levels come out right.
Charlie Edmondson Engineering Inc.
Thanks for your response, Charlie.
It looks like the library is actually named "dig_io.lib" in OrCAD 16.
Some of us have our own personalized 10K, 100K plus ECLIPS ;-)
Easy when you roll your own.
...Jim Thompson
The library seems to be "dig_ecl.lib", not "dig_io.lib".
Do you mean ECLinPS? I cannot find (P)Spice models for ECLinPS.
I rolled my own, but I'm in the chip design business ;-)
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at
There are IBIS models available from OnSemi:
But as far as I know this format is not supported by PSpice.
PSpice does not support IBIS models.
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at
Also, remember, IBIS is purely an I/O model, not any type of form or functionaliity, including internal delays and timing. they are designed for signal integrity purposes, only.
Charlie
Yep. In other words, totally useless for anything other than PCB track analysis.
...Jim Thompson
In article , To-Email- snipped-for-privacy@My-Web-Site.com says...>
They're useful in designing the opposite end, as well. IOW, "purely I/O models". ;-)
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