The phase pulse output is for lock detection. PD2's output is valid in any condition, and when using PD2, PD1 will have a 50% duty cycle when the loop is locked and also when one of the input signals is missing.
I normally just put a window comparator on the PD2 output and use that, since the filtered output pulls to the rail when it's out of lock.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
We have considered using a phase detector and a DDS, 100% digital PLL, inside an FPGA to be able to do i/q demodulation of digitized sinewave signals. It sounded like fun, but we never had a firm application (ie, paying customer) to justify doing it.
In one case, it would have been AC line stuff, 50 or 60 or 400 Hz, fairly narrowband (except aircraft 400 Hz is all over the place.) In another, it would be synchro/LVDT, pretty much audio kind of range.
The digital PLL takes no parts... it's just a heap of VHDL.
-- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
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If you already have an FPGA, sure, dump it in with all the other crap. ;)
A good diode phase detector such as an MPD-1 makes it a pleasure to build first-class PLLs. Lots of output, zilch noise, low and stable offset voltage, easy to drive from logic if you need to. Good medicine.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
I have this particle beam trajectory measurement system where lots of fully digital PLLs are used to follow bunches of protons around a particle accelerator. It spits out the bunch trajectories at an aggregate rate of up to 280M bunch positions per second. All FPGAs. A British firm built it for me. Operators love it. I'm in the process of making a second system for another accelerator.
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eProbably not generally true.
Probably true, but our business is burying the complication so nobody else has to worry about it.
I'm not sure about that as a general statement. I've alway been take with the low power consumption of the Philips/NXP now Xilinx CoolRunner CMOS parts - when you didn't tray and run them too fast - which is why I've got a stick of 15 of them in my cupboard here, waiting for a project to exploit them
Why?
But there's a great deal of manual labour tweaking each example to get it's particular linearity respectable. Physicists have graduate students to do that sort of labour. Engineers designing for production can't afford them.
-- Bill Sloman, Sydney
It passed your sim with slightly different frequencies at each input to create a walking phase shift.
You did need to match the gates. If they were simmed as discrete 7400's then you had to take the 4 on the left from one package.
I know. That's why I was surprised it worked with 8 as quoted:
==========quote========== Newsgroups: alt.binaries.schematics.electronic,sci.electronics.cad,sci.electronics.design,sci.electronics.misc Sent: Monday, August 27, 2001 10:26 PM Subject: Re: Help an Analog Guy with a Digital Problem
|> The internal feedback disabled the pulse too soon. The resulting |> pulse width at the final latch was about 1/2 of what it is with |> feedback from the output (~2.5nS vs 5nS). | |Ok. So was your testing of the last circuit sucessful under full load? |
You bet...you're now in a product...E-Mail for details. =========================
-- Reply in group, but if emailing add one more zero, and remove the last word.
Because driving them in a demodulator loop is a completely needless hassle, and won't do as good a job when you're done. Analogue loops rock. Doing it digitally makes as much sense as emulating an op amp using an ADC, a DAC, and an FPGA, i.e. none.
Not true--read what I wrote above. Inexpensive close-tolerance inductors do just fine.
How are you liking being back in OZ? Run into Phil A. yet?
Cheers
Phil Hobbs
Thanks, Tom! I'll have to try that. Does it have deadband? ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
On a sunny day (Fri, 19 Oct 2012 08:59:28 -0400) it happened Phil Hobbs wrote in :
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mm :-) See my posting in s.e.d today with subject: GPS frequency counter + PLL PIC based
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Why do you think that? The DDS syntheisised sine wave is likely to have a lower jitter than you'd get from most VCOs, and you've got a whole lot better idea of the frequency you are synthesising.
none.
There are occasion when an ADC plus digital signal processing plus a DAC do make sense - as soon as you want a non-linear or - worse - a non-monotonic relationship between input and output. For phase-locked loops this happens quite often - as Floyd M Gardener pointed out, the sort of phase-sensitive detector that gives you the best lock doesn't necessarily get you into lock as fast as you'd like.
The DDS approach comes into its own when you want several sine wave sources at once - for detecting at twice the frequency or both in- phase and in quadrature. The analogue techniques for doing this are no less messy and generally give you a poorer quality sine wave.
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Inexpensive close tolerance varactors don't seem to be as readily available. And the tuning range available is rarely impressive.
Varactors have a roughly hyperbolic capacitance to voltage relationship, so getting the tuning loop critically damped isn't going to be all that easy.
Phil Allison does live in Sydney, but I don't expect to run into him - I did suggest (here) that we get together over a coffee a few years ago but he didn't like the idea.
Oz has been fine so far, but we're not yet entirely out of jet-lag. We've been keeping a low profile. I did apply for two jobs yesterday, but that was more to get my name on the books than in any expectation that I'd get anything. My wife wants to buy a car today, which is going to take a while.
-- Bill Sloman, Nijmegen
and won't
DDSs suck for jitter. Unfiltered, looking at the phase accumulator MSB, they have a full clock of p-p jitter. DAC'd and filtered, into a comparator, it's more complex, but much below the LPF cutoff, you're basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.The real nuisance in a DDS is the damned lowpass filter.
VCOs can be a lot better, and VCXOs hugely better.
-- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
and won't
Slugman is like the yellow line on the road, he's always in the middle, can't take either side but yet, his lines seem to break left or right at every turning post.
He just can't maintain solid facts or lines.
Jamie
alt.binaries.schematics.electronic,sci.electronics.cad,sci.electronics.design,sci.electronics.misc
That exchange was you, me, you. You tested it and according to the email it went into an RFID Tag Chip that reports temperature and pressure of its environment via a 2.4GHz RF Link.
Deadband like a frequency where it doesn't work? Wouldn't there just be an upper limit that depends on the logic speed? I can't teach you anything about that. You'll have to teach me.
Here is the diagram with markings to show the sequence of transitions. The =0 and =1 indicate constant states. The "x" after a number means no further changes are caused by that transition. If you build it with NOR's it is negative-edge triggered.
below: Q(initially) = 0 RESET = 0
/0 SET -----+------------------------| | |NAND>--+ \1 +-------| \5 +--| | /6x |NAND>--+-----+ | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| /4 | | |NAND>-----+ | \3 +-------| +--| Q | |NAND>--+------- /2 +--------------------------------+--| | | | +----------|--+ | | +----------+ | | | _ +--------------------------------+--| | Q | |NAND>-----+---- \3 /2 +-------| +--| |NAND>--+ \3x | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| =1 | | |NAND>-----+--+ | +-------| +--| | =0 | |NAND>--+ =1 RESET -----+------------------------|
below: Q(initially) = 0 RESET = 1
/0 SET -----+------------------------| | |NAND>--+ \1 +-------| \5 +--| | /6x |NAND>--+-----+ | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| /4 | | |NAND>-----+ | \3 +-------| +--| Q | |NAND>--+------- /2 +--------------------------------+--| | | | +----------|--+ | | +----------+ | | | _ +--------------------------------+--| | Q | |NAND>-----+---- \3 /2 +-------| +--| |NAND>--+ =1 | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| =0 | | |NAND>-----+--+ | +-------| +--| | =1 | |NAND>--+ =1 RESET -----+------------------------|
below: Q(initially) = 1 RESET = 0
/0 SET -----+------------------------| | |NAND>--+ \1 +-------| \1 +--| | /2x |NAND>--+-----+ | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| =1 | | |NAND>-----+ | =0 +-------| +--| Q | |NAND>--+------- =1 +--------------------------------+--| | | | +----------|--+ | | +----------+ | | | _ +--------------------------------+--| | Q | |NAND>-----+---- =0 =1 +-------| +--| |NAND>--+ =0 | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| =1 | | |NAND>-----+--+ | +-------| +--| | =0 | |NAND>--+ =1 RESET -----+------------------------|
below: Q(initially) = 1 RESET = 1
/0 SET -----+------------------------| | |NAND>--+ \1 +-------| \1 +--| | /2x |NAND>--+-----+ | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| =1 | | |NAND>-----+ | =0 +-------| +--| Q | |NAND>--+------- =1 +--------------------------------+--| | | | +----------|--+ | | +----------+ | | | _ +--------------------------------+--| | Q | |NAND>-----+---- =0 =1 +-------| +--| |NAND>--+ =1 | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| =0 | | |NAND>-----+--+ | +-------| +--| | =1 | |NAND>--+ =1 RESET -----+------------------------|
-- Reply in group, but if emailing add one more zero, and remove the last word.
much
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Obviously. but what sort of idiot would use one that way? Of course, if your DDS has a 500MHz inrternal clock, 2nsec of jitter might be tolerable.
When I mentioned DDS's earlier in this thread I did mention that you ought to filter the output, but I'd figured that people like you and Phil Hobbs wouldn't need to be reminded.
Actually, as long as the DAC refresh time is shorter than your low pass filter 3dB point, you should do appreciably better than the DAC resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth wave at the DAC refresh rate, and that ought to be a lot faster than the frequency you are interested in, and correspondingly easy to filter out. Four or six poles of low pass filter isn't going to cost anything like as much as the DDS chip.
You should have paid closer attention during the relevant lectures
Only if you find low-pass filters intimidating
VCXO do - however - tend to be rather restricted in the frequencies they can generate.
-- Bill Sloman, Sydney
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rThat's Jamie for you. John Larkin makes a fool of himself and Jamie chimes in to tell us that he too is intellectually limited - as if we didn't already know.
-- Bill Sloman, Sydney
hassle, and won't
Someone who wants to do a lot of DDS PLLs in an FPGA, without going off chip to DACS and filters and comparators.
Of course,
We don't use standard DDS chips very often. We do our own DDS logic in an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC off-chip.
But reminded? By you? I design electronics, and you don't.
The filter takes a lot more area, and does often cost more.
At low frequencies, the filter output settles between phase accumulator code transitions, so the waveform has plateaus. The plateaus trip the comparator at fuzzy levels, so you get a lot of jitter. As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the filter stays in its sweet spot, and divide down after the comparator.I don't understand why ADI makes so many DDS chips, but doesn't make an integrated lowpass filter.
What an ass you are. I got my EE degree before DDS was invented, and you are even older than I am.
How many DDS synthesizers have you designed in the last 10 years? I've done a dozen or so. Hell, have you ever designed a DDS into something?
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
ty much
hassle, and won't
I'm not designing much electronics a the moment, but I didn't need to be reminded that you ought to filter the output of a DDS chip.
If you've built the logic part of the DDS chip into a corner of an FPGA this could well be true. No DAc and no filter sounds like taking economy a little too far.
Only if your low pass filter cuts off at too high a frequency. This does depend on the frequency range you want to cover, and if you were going nuts you might look at ways of moving the 3dB point of the low pass filter around to cover a really wide frequency range.
It's not the plateau that trips the comparator, but the noise on the plateau. A little hysteresis around the comparator might help, but I shouldn't have to point this out to someone with your extravagantly practiced expertise.
The DDS chips would be built with a logic process, while the filter could be expected to be analog. A delay line that could be used to set up a FIR filter could be interesting, but it would use up a lot of pins.
I never got an EE degree, and learned the stuff when I needed it - and read up on it from time to time when I needed more. Low pass filters aren't either complicated or difficult. Why you feel the need to describe them as "damned" escapes me.
None. I've been out of work aka retired for the last ten years, as you well know
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Nothing that got built. I still managed to get my head around the idea that you ought to filter what comes out of the DAC, which doesn't seem to have lodged all that firmly with you.
-- Bill Sloman, Sydney
and won't
Actually, it's quite the opposite. Good show.
Jamie
and won't
I can say one thing about slugman, it does not usually impersonate that often, he's doing very well at being himself, the ASS.
Jamie
much
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Jamie may be slow, but he's persistent. Pity about the direction.
-- Bill Sloman, Sydney
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