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Info on packing regular tree-like structures into rectangles?

Hi, I got thinking about recursive design of circuits in VHDL I created a recursive circuit and got it to simulate correctly but then had the thought that the RTL is a binary tree of similar interconnect with each leaf being the same. When this gets synthesized and layed out I guess that the regularity is lost unless layed out by hand.

If I were to lay this out by hand, are their any existing papers on packing such regular structures into rectangular spaces?

Are there any layout and routing tools designed for such tasks?

Thanks in advance, Paddy.

Reply to
paddy3118
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f'up to comp.lang.vhdl

Hmm .. what do you mean with "recursive circuit"? Eighter the transistors / cells / macroblocks are implemented or not.

You may design a component, that is used by a controller (like a FSM), that realizes a recursive algorithm, but then not the circuit is recursive - only the algorithm is.

Why do you care about regularity of the layout of a digital circuit? Except for signal delays there is no reason to think about the layout - AFAIK.

A HDL is such a wounderful thing, that seperates layout problems from functional behavoir.

Ralf

Reply to
Ralf Hildebrandt

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