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AD8218 spice model is messed up.

Could someone verify for me that the AD8218 spice model is screwed up? The model and data sheet are here

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I'm just trying to reproduce Figure 35 in the datasheet. I'm using the circ uit in Figure 34. I tied Vs and ENB to +IN because Ltspice doesn't like tho se pins floating. I set the shunt resistor to 0.02 ohms, the battery voltag e to 24V, the reference to 1.25v and vary the Load from -5Amps to 5Amps in

0.05amp increments. My results show the part offsetting by twice the refere nce voltage instead of the reference voltage. I can reproduce the graph wit h the 1.25V reference but the datasheet shows a 2.5v reference. Here is the spice netlist.

  • C:\Projects\LIT\N48_TEC_Driver\simulation\AD8218Test.asc XU1 Vpos Vneg Vpos Vref Vpos 0 Vout AD8218 V3 Vpos 0 24 R2 Vneg Vpos 0.02 V1 Vref 0 1.25 I1 N001 0 1 R1 Vneg N001 100 .include AD8218.cir .dc I1 -5 5 0.05 .backanno .end

Thanks

Reply to
wanderer
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e model and data sheet are here

rcuit in Figure 34. I tied Vs and ENB to +IN because Ltspice doesn't like t hose pins floating. I set the shunt resistor to 0.02 ohms, the battery volt age to 24V, the reference to 1.25v and vary the Load from -5Amps to 5Amps i n 0.05amp increments. My results show the part offsetting by twice the refe rence voltage instead of the reference voltage. I can reproduce the graph w ith the 1.25V reference but the datasheet shows a 2.5v reference. Here is t he spice netlist.

I think line 129 is wrong

E03 70 0 Value={ IF( V(ENB) == 0, V(65) + V(600) + .08 + V(ref), IF( V(ENB) != 0, V(65) + V(600) + V(ref), V(65) + V(600) )) }

v(ref) is already added in on line 56. I think the line should read.

E03 70 0 Value={ IF( V(ENB) == 0, V(65) + V(600) + .08, V(65) + V(600 ) ) }

V(ENB) is either equal or not equal to zero, there is no third state and ad ding the V(ref) is redundant. Changing this line gives me the results I exp ect. But maybe I'm expecting the wrong results:)

Reply to
wanderer

Doesn't make it work for me. With + and - inputs strapped, and a common mode stepped voltage applied, and a 2.5V Vref, offset is 2.5V, up to 5.6V applied, then jumps to 5.2V.

Unused inputs grounded via 1T resistors, to make the solver happy.

"if" syntax differs between Pspice and LTspice. That may have something to do with it.

AD is a TI subsidiary, now. I wonder if that subcircuit behaves properly in TINA?

If I get the time, I'll draw the subcircuit out as a schematic. I find that's the easiest way of debugging.

--
"For a successful technology, reality must take precedence  
over public relations, for nature cannot be fooled." 
                                       (Richard Feynman)
Reply to
Fred Abse

I don't like "IF" statements in models or circuits. They provoke convergence issues.

The only time I use "IF" statement is to set Parameters when doing STEP operations. These occur only during establishment (in LT parlance) of the Spice directives, thus have no effect on convergence.

For voltage bounding, I use the following subcircuits...

****************************************************************** .SUBCKT MOST_POS A B OUT PARAMS: W=0.1 E OUT 0 VALUE {(TANH(V(A,B)/(0.679*W))*V(A,B)+V(A)+V(B))/2} .ENDS MOST_POS ****************************************************************** .SUBCKT MOST_NEG A B OUT PARAMS: W=0.1 E OUT 0 VALUE {(TANH(V(B,A)/(0.679*W))*V(A,B)+V(A)+V(B))/2} .ENDS MOST_NEG ******************************************************************

I developed these last year while doing a gig with Synaptics in Rochester, NY. They have actual circuits that perform these functions to cope with multiple supplies and unknown power sequencing events... preventing, as Joerg would say, "PHUT!" ;-)

So I made the subcircuits to speed up simulation of circuits containing many of these elements.

(These should work just fine in LTspice, as well as in any other Spice variant which adheres to Berkeley Spice basics... except some may need a name change to a "B" source... I think LTspice handles both syntaxes.) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

LTspice handles quite a few syntaxes (syntaces?) that aren't in the manual.

The nice thing about standards is that there are so many to choose from...

--
"For a successful technology, reality must take precedence  
over public relations, for nature cannot be fooled." 
                                       (Richard Feynman)
Reply to
Fred Abse

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"B"-style syntax is basic to all Spice variants.

I believe PSpice first introduced the EVALUE form, but LTspice and several other variants recognize that syntax. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

I think syntaxes is right. But it sound too much like sin taxes.

[...] 
--
Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

Only in certain counties in Nevada...

-- "For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)

Reply to
Fred Abse

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