I am using XPS 8.2.01i to create a V4FX12 design for the the xilinx ML403 board. I used bsb to create a design with a 300 Mhz PPC, a 100 Mhz PLB and the PLB_DDR interface. No internal block ram. It got that to build just fine, after figuring out to comment out a line in etc/fast_runtime.opt to deal with no block ram, as specified in answer
23657. Next, tried adding my own custom DCR bus, and the DCR based interrupt controller. When I do this, I got the following error:...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC... Sourcing tcl file C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v1_12_a/data/ddr_v2_1_0.tcl ... Sourcing tcl file C:/EDK/hw/XilinxProcessorIPLib/pcores/intc_core_v1_00_c/data/intc_core_v2_1_0.tc l ...
Performing System level DRCs on properties...
Check platform configuration ... plb_v34 (plb) - C:\dimatix\custom403M\system.mhs line 78 - 2 master(s) :
1 slave(s)dcr_v29 (dcr_v29_0) - C:\dimatix\custom403M\system.mhs line 197 - 1 master(s) : 1 slave(s)
Check port drivers...
Performing Clock DRCs...
This application has discovered an exceptional condition from which it cannot recover. make: *** [implementation/system.bmm] Error 1
Done!
I tried building a design up from scratch again, this time leaving out my custom peripheral and just adding the DCR interrupt controller. Again I get the same error. Does anyone have an idea what I could be doing wrong? Is the sys_clk_s signal the correct clock to use for the DCR bus? Some of the interrupt controller pins are not hooked up, but even before when they were hooked up I got this problem. It looks like the problem happens when it is doing a DRC on the clocks. I couldn't find anything searching the xilinx answer database. Thanks in advance for any hints you can offer.
Here is a copy of the mhs file:
# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 8.2.01 Build EDK_Im_Sp1.3 # Tue Oct 24 23:36:16 2006 # Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 # Family: virtex4 # Device: xc4vfx12 # Package: ff668 # Speed Grade: -10 # Processor: PPC 405 # Processor clock frequency: 300.000000 MHz # Bus clock frequency: 100.000000 MHz # Debug interface: FPGA JTAG # Instruction Cache: 16 KB # Total Off Chip Memory : 64 MB # - DDR_SDRAM_32Mx32 = 64 MB ###############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_DD_SDRAM_64Mx32_DDR_Clk_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk, DIR = O PORT fpga_0_DDRSDRAM_64Mx32_DDR_Clkn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn, DIR = O PORT fpga_0_DDR_DRAM_64Mx32_DDR_Addr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr, DIR = O, VEC = [0:12] PORT fpga_0_DDR_SRAM_64Mx32_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr, DIR = O, VEC = [0:1] PORT fpga_0_DDR_SDAM_64Mx32_DDR_CASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn, DIR = O PORT fpga_0_DDR_SDRM_64Mx32_DDR_CKE_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE, DIR = O PORT fpga_0_DDR_SDRA_64Mx32_DDR_CSn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn, DIR = O PORT fpga_0_DDR_SDRAM64Mx32_DDR_RASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn, DIR = O PORT fpga_0_DDR_SDRAM_4Mx32_DDR_WEn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn, DIR = O PORT fpga_0_DDR_SDRAM_6Mx32_DDR_DM_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DM, DIR = O, VEC = [0:3] PORT fpga_0_DDR_SDRAM_64x32_DDR_DQS_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS, DIR = IO, VEC = [0:3] PORT fpga_0_DDR_SDRAM_64M32_DDR_DQ_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ, DIR = IO, VEC = [0:31] PORT fpga_0_DDR_CLK_FB = dr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 PORT sys_clk_pin = dcm_clk_, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
BEGIN ppc405_virtex4 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 1.01.a BUS_INTERFACE JTAGPPC = jtagppc_0_0 BUS_INTERFACE IPLB = plb BUS_INTERFACE DPLB = plb BUS_INTERFACE MDCR = dcr_v29_0 PORT PLBCLK = sys_clk_s PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT CPMC405CLOCK = proc_clk_s END
BEGIN jtagppc_cntlr PARAMETER INSTANCE = jtagppc_0 PARAMETER HW_VER = 2.00.a BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 END
BEGIN proc_sys_reset PARAMETER INSTANCE = reset_block PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Ext_Reset_In = sys_rst_s PORT Slowest_sync_clk = sys_clk_s PORT Chip_Reset_Req = C405RSTCHIPRESETREQ PORT Core_Reset_Req = C405RSTCORERESETREQ PORT System_Reset_Req = C405RSTSYSRESETREQ PORT Rstc405resetchip = RSTC405RESETCHIP PORT Rstc405resetcore = RSTC405RESETCORE PORT Rstc405resetsys = RSTC405RESETSYS PORT Bus_Struct_Reset = sys_bus_reset PORT Dcm_locked = dcm_1_lock END
BEGIN plb_v34 PARAMETER INSTANCE = plb PARAMETER HW_VER = 1.02.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT PLB_Clk = sys_clk_s END
BEGIN plb_ddr PARAMETER INSTANCE = DDR_SDRAM_64Mx32 PARAMETER HW_VER = 1.12.a PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1 PARAMETER C_PLB_CLK_PERIOD_PS = 10000 PARAMETER C_REG_DIMM = 0 PARAMETER C_DDR_TMRD = 20000 PARAMETER C_DDR_TWR = 20000 PARAMETER C_DDR_TRAS = 60000 PARAMETER C_DDR_TRC = 90000 PARAMETER C_DDR_TRFC = 80000 PARAMETER C_DDR_TRCD = 30000 PARAMETER C_DDR_TRRD = 15000 PARAMETER C_DDR_TRP = 30000 PARAMETER C_DDR_TREFC = 70300000 PARAMETER C_DDR_TREFI = 7800000 PARAMETER C_DDR_AWIDTH = 13 PARAMETER C_DDR_COL_AWIDTH = 9 PARAMETER C_DDR_BANK_AWIDTH = 2 PARAMETER C_DDR_DWIDTH = 32 PARAMETER C_MEM0_BASEADDR = 0xfc000000 PARAMETER C_MEM0_HIGHADDR = 0xffffffff BUS_INTERFACE SPLB = plb PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn PORT Clk90_in = clk_90_s PORT Clk90_in_n = clk_90_n_s PORT PLB_Clk_n = sys_clk_n_s PORT DDR_Clk90_in = ddr_clk_90_s PORT DDR_Clk90_in_n = ddr_clk_90_n_s END
BEGIN util_vector_logic PARAMETER INSTANCE = sysclk_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = sys_clk_s PORT Res = sys_clk_n_s END
BEGIN util_vector_logic PARAMETER INSTANCE = clk90_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = clk_90_s PORT Res = clk_90_n_s END
BEGIN util_vector_logic PARAMETER INSTANCE = ddr_clk90_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = ddr_clk_90_s PORT Res = ddr_clk_90_n_s END
BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_DIVIDE = 1 PARAMETER C_CLKFX_MULTIPLY = 3 PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_DFS_FREQUENCY_MODE = HIGH PARAMETER C_DLL_FREQUENCY_MODE = LOW PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLK90 = clk_90_s PORT CLKFX = proc_clk_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock END
BEGIN dcm_module PARAMETER INSTANCE = dcm_1 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_DLL_FREQUENCY_MODE = LOW PARAMETER C_PHASE_SHIFT = 12 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED PARAMETER C_EXT_RESET_HIGH = 0 PORT CLKIN = ddr_feedback_s PORT CLK90 = ddr_clk_90_s PORT CLK0 = dcm_1_FB PORT CLKFB = dcm_1_FB PORT RST = dcm_0_lock PORT LOCKED = dcm_1_lock END
BEGIN dcr_v29 PARAMETER INSTANCE = dcr_v29_0 PARAMETER HW_VER = 1.00.a END
BEGIN dcr_intc PARAMETER INSTANCE = dcr_intc_0 PARAMETER HW_VER = 1.00.b BUS_INTERFACE SDCR = dcr_v29_0 PORT DCR_Clk = sys_clk_s PORT DCR_Rst = sys_bus_reset END