I have a Verilog module that has been synthesized but not mapped. I would like to be able to reuse the NGC file in another design but Xilinx ISE 7 does not seem to want to read in a NGC file as one of the input files. ISE 7 also does not seem to generate a usable EDN file.
What is the recommended netlist format for IP core/design reuse ?
Thanks.
Jim