Writing a Xilnx testbench

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Hei,

When using the Xilins HDL bencher, the memory usage is running up to
1GB. I understood this is a known problem and it is suggested to write
your own test bench. Can anybody give me a clue on how to do this? On
the Xilinx site I was not able to find a description on this, but that
probably is caused by the fact that there is such a huge amount of data
there. To be more specific, I am looking for information on for example
adjusting/sizing simulation time, preferably with example files. All
quite basic, I think.

Thanks,

Aart

Re: Writing a Xilnx testbench
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Check out www.opencores.org. Many, many free IP cores, most
with excellent test benches. Also a few white papers ...

Regards,
rudi              
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Re: Writing a Xilnx testbench
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Read The Book: Janick Bergeron's _Writing Testbenches: Functional
Verification of HDL Models_.  See here:
http://www.janick.bergeron.com/wtb/default.htm

--a

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