Will FPGAs suit my need?

You will be better off starting out with a CPLD. These are stand alone devices that do not require an external configuration memory and are generally much cheaper than FPGA's, typically under $5.

Have a look at

Download Alteras' free software and start experimenting! Altera software supports schematic entry and the included libraries include most of the 7400 series to get you started.

Good luck!

Icky

Austin

FPGA. Get one of the Xilinx development boards and download the WebPack free software. Expect a decently nasty learning curve, but then you'll be able to do amazing stuff. Need a dozen 32-bit up/down counters? Twenty 16x16 multipliers? No sweat.

John

The Xilinx WebPack includes a schematic capture input that allows you to use 7400 chips to represent your logic. You can play with it without buying any hardware.

As for hardware, a CPLD is tens to hundreds (in a few cases thousands) of flops which can be connected with quite a bit (equivalent of hundreds or thousands of 7400 series chips) of combinatoral logic. They're generally flash programmable and available in human-solderable packages.

An FPGA is thousands to tens or hundreds of thousands of flops and connecting logic. They require some kind of external programming (like a flash eeprom) and the larger parts are only available in fine pitch or BGA type packages.

FPGAs will do this, as will CPLDs as others have suggested. There are also FLASH FPGAs, and CPLDs wih FPGA fabric, like MaxII and MachXO, so there are plenty of HW choices.

Your real challenge is deciding just how you are most comfortable doing this bit: "I would like actual control of the connections between the chips"

- entry schemes range from Schematic, to Boolean Eqn (Abel/CUPL/WinPLACE)s, to HDLs like Verilog orVHDL.

Some CPLD vendors are Actel, Altera, Atmel, ICT(anachip), Cypress, Lattice, Xilinx

What is your supply voltage range ? - that will filter significantly the PLD candidates

-jg

Thanks alot for your responses they've been quite helpful! It seems FPGAs or CLPDs are the way forward.

Much appreciated! :-) Nick

This is a dangerous advice. 7400 logic is often used in an asynchronous way. Building a flip-flip out of NOR/NAND gates will work with 7400 series logic, but in an FPGA it most probably won't.

Does that still stand with CPLDs?

Nick

Yes it could, dependent on construction and how the synthesis is forced - but then you would use a 7474 - wouldn't you?

Cross coupled nand set-resets work fine for both Altera FPGA and CPLD's.

Icky

Indeed they do; but WHERE are you intending to use one of them?

If the set and reset signals you're feeding into them are synchronous (i.e. they are flip-flop outputs) then it makes at least as much sense to implement the SR in a synchronous style. No need for that combinational feedback loop, which will cause (at the very least) warning messages from the timing analyzer.

If the set and reset signals are asynchronous, then they may suffer decoding glitches that could give undesirable tripping of your S-R latch if you're unlucky (and, as we all know, your luck generally runs out about two days after you've shipped the product to the most important customer). So you probably need to resynchronise those signals anyway, which means that you could just as easily have used a fully synchronous S-R implementation.

So... in almost any realistic situation, the cross-coupled SR latch is either unnecessary or undesirable. It is an example of an asynchronous state machine - admittedly a fairly simple example, and one that's relatively easy to get right - and, like all asynchronous state machines, it requires special techniques to use it properly and to avoid tools making unacceptable optimisations to it.

Flame away, I'm sure there are some interesting contrary points of view!

Streuth!

Actually the only place I WOULD use it is for an asynchronous front end interface to a switch, i.e. used as a PROPER switch debouncer with a SPCO switch. I was using it as an illustration!

Icky

It depends on the architecture. CPLD are usually based on an output/flip-flop element preceeded by a 'sum of products' element (larger CPLDs use muxes/switch matrices to get some routing flexibilty). Because the timing to the output is well defined, it can be used as an input to a 'sum of products' element to create an asynchronous latch.

An FPGA usually consists of small look-up tables to contain the logic. Each look-up table adds delay. If you have a bunch of logic around a nand/nor based flip-flop, the synthesizer will spread the logic over several look-up tables. The order and timing depends on how the optimizer and router place the logic. It may be that the reset or set conditions don't last long enough to achieve a stable output which may cause all kinds of weird effects (oscillating, not working, sometimes working) and each time you route an FPGA, the placement of the logic is different so the outcome of asynchronous logic may be different.

Hi Jonathan, What about a 4046 type two PLL phase comparator?

Actually, this is better inplemented as two FFs*, one clocked by the VCO, one by the Reference frequency, but I still claim it's a 'realistic situation'! :-) Cheers, Symon.

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  look at fig.2.

You need SPLD's simple programmable logic devices like the 22v10 or 16v8 (which I am using for my designs). You can get them at jameco,allect or better yet: EBAY