Virtex2P: lock down DCM and Global buffer

Hi, I have a design targeting V2P7 chip, in PAR there is an error saying that my design uses more global buffers than it can be allowed, and stating that each region can only have 1 global buffer, either primary ot secondary.

V2P7 has in total 16 global buffers. In this design I have 10 global buffers used, but I have another design using 9 buffers and works great. Both designs use 4 DCM, and the only difference between the two design is I use one more global buffer to connect the 4th DCM clk0.

I am trying to lock down the DCM and global buffers manually in UCF, but got bad luck. In FPGA editor I can see that in 9-buffer-design, the

4th DCM is at X0Y0 and on the same side of the FPGA, global buffer 7S, 6P and 5S are unused. So what I do is like this in UCF: 1) lock all 4 DCM and 9 buffers as they are done in 9-buffer-design 2) lock the 10th buffer to 6P.

But I get the same error from PAR, then I tried 7S, still same.

I wonder if it is right of my doing this way, although I will try 5S.

Thanks so much.

Hello John,

The restriction is that each primary and secondary clock buffer pair can not drive clock loads within the same clock region. This translates to eight possible clocks per clock region. The DCMs count as clock loads so this rule applies to them too. Perhaps you have two DCMs LOC'd such that there is a primary secondary clock conflict?

One way to debug this issue is to load the mapped NCD in FPGA Editor where it will display all LOC'd logic as already placed. By hi-lighting each clock net in turn, you'll be able to see which clock regions each clock net is using. You can tell where the clock region boundaries are by turning on the long line display and noting where the long lines are partitioned.

If this doesn't help, please post the complete PAR error message. Your description doesn't correspond to any message I would expect to see from the clock placer.

Thanks, Bret

John Black wrote: